On Mon, 8 Feb 2021 at 18:58, Richard Henderson <richard.hender...@linaro.org> wrote: > > On 2/8/21 10:28 AM, Peter Maydell wrote: > > On Mon, 8 Feb 2021 at 17:53, Peter Maydell <peter.mayd...@linaro.org> wrote: > >> The AAPCS says that q4-q7 are preserved across calls. > > > > Speaking of which, doesn't that mean we also need to > > save and restore q4-q7 in tcg_target_qemu_prologue() > > if we might be generating neon insns? (It doesn't look like > > aarch64's prologue does this, which seems like a bug.) > > I just put them on the reserved list so that they don't get used. > > > tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V8); > ... > > tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
I'm confused. That's not the reserved list, it's the call-clobber list, and it's not putting the registers on the list, it's taking them off it. (The code looks correct for setting up the clobber list: we start with "everything is clobbered" and then remove the callee-saves regs. But the AArch64 PCS says that only the bottom 64-bits of v8-v15 are saved, so in fact I don't think we can mark them as not-call-clobbers unless we're forcing the vector code to only use 64-bits of vector registers.) The only things on the reserved_regs list for aarch64 are integer regs as far as I can see (sp, fp, x18, x30, v31). -- PMM
