On Tue, Jan 12, 2021 at 1:55 AM <frank.ch...@sifive.com> wrote:
>
> From: LIU Zhiwei <zhiwei_...@c-sky.com>
>
> Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
> Signed-off-by: Frank Chang <frank.ch...@sifive.com>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu_bits.h | 7 +++++++
> target/riscv/csr.c | 21 +++++++++++++++++++++
> 2 files changed, 28 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 8edf81692e6..2538580a62a 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -60,9 +60,16 @@
> #define CSR_VSTART 0x008
> #define CSR_VXSAT 0x009
> #define CSR_VXRM 0x00a
> +#define CSR_VCSR 0x00f
> #define CSR_VL 0xc20
> #define CSR_VTYPE 0xc21
>
> +/* VCSR fields */
> +#define VCSR_VXSAT_SHIFT 0
> +#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT)
> +#define VCSR_VXRM_SHIFT 1
> +#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT)
> +
> /* User Timers and Counters */
> #define CSR_CYCLE 0xc00
> #define CSR_TIME 0xc01
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6eda5bacb7c..4ac1ed8cfa8 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -335,6 +335,26 @@ static int write_vstart(CPURISCVState *env, int csrno,
> target_ulong val)
> return 0;
> }
>
> +static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
> + return 0;
> +}
> +
> +static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
> + return -1;
> + }
> + env->mstatus |= MSTATUS_VS;
> +#endif
> +
> + env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
> + env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
> + return 0;
> +}
> +
> /* User Timers and Counters */
> static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
> {
> @@ -1397,6 +1417,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_VSTART] = { vs, read_vstart, write_vstart
> },
> [CSR_VXSAT] = { vs, read_vxsat, write_vxsat
> },
> [CSR_VXRM] = { vs, read_vxrm, write_vxrm
> },
> + [CSR_VCSR] = { vs, read_vcsr, write_vcsr
> },
> [CSR_VL] = { vs, read_vl
> },
> [CSR_VTYPE] = { vs, read_vtype
> },
> /* User Timers and Counters */
> --
> 2.17.1
>
>
