On 1/17/21 11:46 PM, Philippe Mathieu-Daudé wrote:
> Hi Jiaxun,
>
> On 1/14/21 2:31 AM, Jiaxun Yang wrote:
>> loongson3_virt has KVM SMP support in kenrel.
>> This patch adds TCG SMP support by enable IPI controller
>> for machine.
>>
>> Note that TCG SMP can only support up to 4 CPUs as we
>> didn't implement multi-node support.
>>
>> Signed-off-by: Jiaxun Yang <jiaxun.y...@flygoat.com>
>> ---
>> hw/mips/loongson3_bootp.h | 1 +
>> hw/mips/loongson3_virt.c | 20 +++++++++++++++++++-
>> hw/mips/Kconfig | 1 +
>> 3 files changed, 21 insertions(+), 1 deletion(-)
...
>> + if (!kvm_enabled()) {
>> + /* IPI is handled by kernel for KVM */
>> + DeviceState *ipi;
>> + ipi = qdev_new(TYPE_LOONGSON_IPI);
>> + sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
>> + sysbus_mmio_map(SYS_BUS_DEVICE(ipi), 0,
>> + virt_memmap[VIRT_IPIS].base + IPI_REG_SPACE *
>> i);
>> + sysbus_connect_irq(SYS_BUS_DEVICE(ipi), 0, cpu->env.irq[6]);
>
> While this works, it is very fragile. If multiple IRQs share the same
> CPU pin, the better way is to use an OR gate (modeled as TYPE_OR_IRQ
> device).
Doh I misread, I thought it was a signal from a core to the IPI, but
this is a signal from each IPI to its CPU core, so this is good.
>
>> }
>>
>> for (ip = 0; ip < 4 ; ip++) {
>> int pin = i * 4 + ip;
>> sysbus_connect_irq(SYS_BUS_DEVICE(liointc),
>> pin, cpu->env.irq[ip + 2]);
>
> Oops, we already use it without OR gate :/
Ditto, I misread, code is correct (4 outputs from LIOINTC to
4 input of CPU core).
>
> Regards,
>
> Phil.
>
