On 1/12/21 11:28 PM, Eduardo Habkost wrote:
> On Tue, Jan 12, 2021 at 11:15:38PM +0100, Philippe Mathieu-Daudé wrote:
>> On 1/12/21 9:44 PM, Richard Henderson wrote:
>>> On 1/12/21 8:41 AM, Philippe Mathieu-Daudé wrote:
>>>> Some ISA use a dot in their opcodes. Allow the decodetree
>>>> script to process them. The dot is replaced by an underscore
>>>> in the generated code.
>>>
>>> Given that you then have to remember to use '_' on the C side, what
>>> advantage
>>> does this give?
>>
>> The direct advantage is you can copy/paste the opcode in a PDF viewer
>> without having to edit it :)
>>
>> See i.e. some Loongson opcodes [*]:
>>
>> MULT.G 011100 ..... ..... ..... 00000 010000 @rs_rt_rd
>> DMULT.G 011100 ..... ..... ..... 00000 010001 @rs_rt_rd
>> MULTU.G 011100 ..... ..... ..... 00000 010010 @rs_rt_rd
>> DMULTU.G 011100 ..... ..... ..... 00000 010011 @rs_rt_rd
>>
>> DIV.G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd
>> DDIV.G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
>> DIVU.G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd
>> DDIVU.G 011100 ..... ..... ..... 00000 010111 @rs_rt_rd
>>
>> MOD.G 011100 ..... ..... ..... 00000 011100 @rs_rt_rd
>> DMOD.G 011100 ..... ..... ..... 00000 011101 @rs_rt_rd
>> MODU.G 011100 ..... ..... ..... 00000 011110 @rs_rt_rd
>> DMODU.G 011100 ..... ..... ..... 00000 011111 @rs_rt_rd
>>
>> The other - remote - advantage I see is when using a disassembler
>> based on decodetree (as AVR does), the opcode displayed also matches
>> the specs. We are not yet there with MIPS, but I have something in
>> progress...
>
> Interesting. So, the decodetree format is not used exclusively
> inside the QEMU source tree, but also by other projects? Is
> there a specification somewhere else?
"as AVR does in QEMU", see commit 9d8caa67a24
("target/avr: Add support for disassembling via option '-d in_asm'").
What seduces me with decodetree is we don't need to match QEMU
instruction class with each CPU capabilities. IOW we can use the
same decoder for TCG and disassembly, and the disassembly matches
the instruction set of the CPU (with all the specific instructions).
Currently some specific opcodes are displayed as generic ones (or
as unknown via hexadecimal value). Unfortunately not something we
can show with QEMU AVR target because the ISA is very simple.
Regards,
Phil.
