From: Leif Lindholm <l...@nuviainc.com>
The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
Extend the clidr field to be able to hold this context.
Signed-off-by: Leif Lindholm <l...@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnog...@gmail.com>
Message-id: 20210108185154.8108-3-l...@nuviainc.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
target/arm/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ed3e9fe2e4e..fdbfcec2b09 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -938,7 +938,7 @@ struct ARMCPU {
uint32_t id_afr0;
uint64_t id_aa64afr0;
uint64_t id_aa64afr1;
- uint32_t clidr;
+ uint64_t clidr;
uint64_t mp_affinity; /* MP ID without feature bits */
/* The elements of this array are the CCSIDR values for each cache,
* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
--
2.20.1
