On Thu, 17 Dec 2020 at 00:45, Hao Wu <wuhao...@google.com> wrote: > > This patch allows NPCM7XX CLK module to compute clocks that are used by > other NPCM7XX modules. > > Add a new struct NPCM7xxClockConverterState which represents a > single converter. Each clock converter in CLK module represents one > converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter > takes one or more input clocks and converts them into one output clock. > They form a clock hierarchy in the CLK module and are responsible for > outputing clocks for various other modules in an NPCM7XX SoC. > > Each converter has a function pointer called "convert" which represents > the unique logic for that converter. > > The clock contains two initialization information: ConverterInitInfo and > ConverterConnectionInfo. They represent the vertices and edges in the > clock diagram respectively. > > Reviewed-by: Havard Skinnemoen <hskinnem...@google.com> > Reviewed-by: Tyrone Ting <kft...@nuvoton.com> > Signed-off-by: Hao Wu <wuhao...@google.com>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
