On Thu, Jan 7, 2021 at 1:11 AM Atish Patra <atish.pa...@wdc.com> wrote:
>
> Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is
> lesser. However, Linux kernel can address only 1GB of memory for RV32.
> Thus, it can not map anything beyond 3GB (assuming 2GB is the starting
> address).
> As a result, it can not process DT and panic if opensbi dynamic firmware
> is used. While at it, place the DTB further away to avoid in memory placement
> issues in future.
>
> Fix this by placing the DTB at 16MB from 3GB or end of DRAM whichever is
> lower.
>
> Fixes: 66b1205bc5ab ("RISC-V: Copy the fdt in dram instead of ROM")
>
> Reviewed-by: Bin Meng <bin.m...@windriver.com>
> Tested-by: Bin Meng <bin.m...@windriver.com>
> Signed-off-by: Atish Patra <atish.pa...@wdc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> Changes from v2->v1
> 1. Added the fixes tag and updated aligned down address to 16MB.
> ---
> hw/riscv/boot.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index d62f3dc7581e..2ed23c7e9849 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -202,11 +202,11 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t
> mem_size, void *fdt)
> /*
> * We should put fdt as far as possible to avoid kernel/initrd
> overwriting
> * its content. But it should be addressable by 32 bit system as well.
> - * Thus, put it at an aligned address that less than fdt size from end of
> - * dram or 4GB whichever is lesser.
> + * Thus, put it at an 16MB aligned address that less than fdt size from
> the
> + * end of dram or 3GB whichever is lesser.
> */
> - temp = MIN(dram_end, 4096 * MiB);
> - fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
> + temp = MIN(dram_end, 3072 * MiB);
> + fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
>
> fdt_pack(fdt);
> /* copy in the device tree */
> --
> 2.25.1
>
>
