On 1/4/21 11:11 PM, Philippe Mathieu-Daudé wrote: > Philippe Mathieu-Daud=C3=A9 (15): > target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment > target/mips/mips-defs: Reorder CPU_MIPS5 definition > target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 > target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() > hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() > target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 > target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 > target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 > target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 > target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 > target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 > target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 > target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 > target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 > target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 > > target/mips/cpu.h | 5 + > target/mips/internal.h | 8 +- > target/mips/mips-defs.h | 46 +-- > hw/mips/boston.c | 6 +- > linux-user/mips/cpu_loop.c | 6 +- > target/mips/cp0_helper.c | 18 +- > target/mips/cp0_timer.c | 4 +- > target/mips/cpu.c | 6 +- > target/mips/fpu_helper.c | 4 +- > target/mips/helper.c | 12 +- > target/mips/translate.c | 620 +++++++++++++++---------------- > target/mips/translate_init.c.inc | 14 +- > 12 files changed, 370 insertions(+), 379 deletions(-)
Series queued to mips-next.
