On 1/5/21 12:30 AM, Richard Henderson wrote: > On 1/4/21 12:11 PM, Philippe Mathieu-Daudé wrote: >> MIPS 64-bit ISA is introduced with MIPS3. >> >> Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA, >> and the cpu_type_is_64bit() method to check if a CPU supports >> this ISA (thus is 64-bit). >> >> Suggested-by: Jiaxun Yang <jiaxun.y...@flygoat.com> >> Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> >> --- >> target/mips/cpu.h | 5 +++++ >> target/mips/mips-defs.h | 4 +++- >> 2 files changed, 8 insertions(+), 1 deletion(-) > > I still don't understand this as an alias, as opposed to a separate bit. > (ISA_MIPS3 | CPU_MIPS64R6) does not make sense, because R6 removes > instructions.
I now understand your concern. I based the decodetree logic on the R6 ISA manual, decoding the bits from the more recent feature (a leaf) to the root, following this tree: https://images.anandtech.com/doci/8457/MIPS%20ISA%20Evolution.JPG (2.3 Evolution of the Architecture). Also "2.1 Historical Perspective": In the MIPS IIITM ISA, 64-bit integers and addresses were added to the instruction set. [...] The MIPS32 Release 6 ISA maintains backward-compatibility, with the exception of a few rarely used instructions, though the use of trap-and-emulate or trap-and-patch; all pre-Release 6 binaries can execute under binary translation. [...] The MIPS64 Architecture is based on the MIPS V ISA and is backward compatible with the MIPS32 Architecture. > But if this is an intermediate step, As this isn't planned as intermediate step, I'll try to keep CPU_MIPS64 as a separate bit and post the result. Thanks for reviewing! Phil.
