On Wed, 23 Dec 2020 17:08:30 +0800
Jiahui Cen <cenjia...@huawei.com> wrote:
> AML needs Address Translation offset to describe how a bridge translates
> addresses accross the bridge when using an address descriptor, and
> especially on ARM, the translation offset of pio resource is usually
> non zero.
could you point out where in patch [8/8] it becomes non zero?
>
> Therefore, it's necessary to pass offset for pio, mmio32, mmio64 and bus
> number into build_crs.
>
> Signed-off-by: Jiahui Cen <cenjia...@huawei.com>
> ---
> hw/acpi/aml-build.c | 18 ++++++++++--------
> hw/i386/acpi-build.c | 3 ++-
> hw/pci-host/gpex-acpi.c | 3 ++-
> include/hw/acpi/aml-build.h | 4 +++-
> 4 files changed, 17 insertions(+), 11 deletions(-)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index f976aa667b..7b6ebb0cc8 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -2076,7 +2076,9 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker,
> GArray *tcpalog)
> tpm2_ptr, "TPM2", table_data->len - tpm2_start, 4, NULL,
> NULL);
> }
>
> -Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
> +Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t
> io_offset,
> + uint32_t mmio32_offset, uint64_t mmio64_offset,
> + uint16_t bus_nr_offset)
> {
> Aml *crs = aml_resource_template();
> CrsRangeSet temp_range_set;
> @@ -2189,10 +2191,10 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet
> *range_set)
> for (i = 0; i < temp_range_set.io_ranges->len; i++) {
> entry = g_ptr_array_index(temp_range_set.io_ranges, i);
> aml_append(crs,
> - aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
> - AML_POS_DECODE, AML_ENTIRE_RANGE,
> - 0, entry->base, entry->limit, 0,
> - entry->limit - entry->base + 1));
> + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED,
> + AML_POS_DECODE, AML_ENTIRE_RANGE,
> + 0, entry->base, entry->limit, io_offset,
> + entry->limit - entry->base + 1));
> crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
> }
>
> @@ -2205,7 +2207,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet
> *range_set)
> aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
> AML_MAX_FIXED, AML_NON_CACHEABLE,
> AML_READ_WRITE,
> - 0, entry->base, entry->limit, 0,
> + 0, entry->base, entry->limit,
> mmio32_offset,
> entry->limit - entry->base + 1));
> crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
> }
> @@ -2217,7 +2219,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet
> *range_set)
> aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
> AML_MAX_FIXED, AML_NON_CACHEABLE,
> AML_READ_WRITE,
> - 0, entry->base, entry->limit, 0,
> + 0, entry->base, entry->limit,
> mmio64_offset,
> entry->limit - entry->base + 1));
> crs_range_insert(range_set->mem_64bit_ranges,
> entry->base, entry->limit);
> @@ -2230,7 +2232,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet
> *range_set)
> 0,
> pci_bus_num(host->bus),
> max_bus,
> - 0,
> + bus_nr_offset,
> max_bus - pci_bus_num(host->bus) + 1));
>
> return crs;
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index f18b71dea9..f56d699c7f 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -1360,7 +1360,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
> }
>
> aml_append(dev, build_prt(false));
> - crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
> &crs_range_set);
> + crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
> &crs_range_set,
> + 0, 0, 0, 0);
> aml_append(dev, aml_name_decl("_CRS", crs));
> aml_append(scope, dev);
> aml_append(dsdt, scope);
> diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
> index 7f20ee1c98..11b3db8f71 100644
> --- a/hw/pci-host/gpex-acpi.c
> +++ b/hw/pci-host/gpex-acpi.c
> @@ -168,7 +168,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig
> *cfg)
> * 1. The resources the pci-brige/pcie-root-port need.
> * 2. The resources the devices behind pxb need.
> */
> - crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
> &crs_range_set);
> + crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
> &crs_range_set,
> + cfg->pio.base, 0, 0, 0);
> aml_append(dev, aml_name_decl("_CRS", crs));
>
> acpi_dsdt_add_pci_osc(dev);
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index e727bea1bc..54a5aec4d7 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -452,7 +452,9 @@ void crs_replace_with_free_ranges(GPtrArray *ranges,
> void crs_range_set_init(CrsRangeSet *range_set);
> void crs_range_set_free(CrsRangeSet *range_set);
>
> -Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set);
> +Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t
> io_offset,
> + uint32_t mmio32_offset, uint64_t mmio64_offset,
> + uint16_t bus_nr_offset);
>
> void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
> uint64_t len, int node, MemoryAffinityFlags flags);
