On 12/29/20 6:26 AM, Jiaxun Yang wrote: > 在 2020/12/29 上午11:26, BALATON Zoltan 写道: >> Hello, >> >> While continuing with part two of my vt82c686b clean ups I've tried to >> implement SMBus IO base configuration in the vt82c686b-pm part that >> I've already done for vt8231 for pegasos2 and it should be the same >> for 686B. (In short, writing address to pm config 0x90 sets base >> address of smbus regs and bit 0 of 0xd2 enables/disables it.) This is >> what the firmware does first and it would allow removing hard coded >> 0xeee1 value and the property to set it and then I could reuse the >> same PM part in VT8231. >> > [...] >> >> Any idea what this is trying to do and how to fix it? > > It's trying to translate Bonito style PCI config space r/w to standard PCI > config space R/W. > > A quick galance told me change BONITO_PCICONF_REG_MASK to 0xff > may help.
Per the datasheet section "5.7.5. Accessing PCI configuration space" 0xfc is the correct value, but the register number starts at the 2nd bit. So this is not a write access to register 0xd2 but 0x34? If you can test, this is the snippet I plan to send later: -- >8 -- diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c index a99eced0657..65953766dd0 100644 --- a/hw/pci-host/bonito.c +++ b/hw/pci-host/bonito.c @@ -189,3 +189,3 @@ FIELD(BONGENCFG, PCIQUEUE, 12, 1) #define BONITO_PCICONF_REG_MASK 0xFC -#define BONITO_PCICONF_REG_OFFSET 0 +#define BONITO_PCICONF_REG_OFFSET 2 --- > > Thanks. > > - Jiaxun > >> >> Regards, >> BALATON Zoltan > >
