Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Bin Meng <bin.m...@windriver.com> Tested-by: Bin Meng <bin.m...@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabb...@google.com> Acked-by: Palmer Dabbelt <palmerdabb...@google.com> --- target/riscv/cpu.h | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0a326c843..9c064f3094 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -44,6 +44,12 @@ #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#if defined(TARGET_RISCV32) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 +#elif defined(TARGET_RISCV64) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 +#endif + #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) -- 2.29.2