On 12/15/20 8:01 PM, frank.ch...@sifive.com wrote:
> From: Kito Cheng <kito.ch...@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.ch...@sifive.com>
> Signed-off-by: Frank Chang <frank.ch...@sifive.com>
> ---
> target/riscv/insn32-64.decode | 4 +++
> target/riscv/insn32.decode | 7 +++-
> target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++++++++
> target/riscv/translate.c | 42 ++++++++++++++++++++++
> 4 files changed, 99 insertions(+), 1 deletion(-)
> create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
> +static void gen_ctzw(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32));
> + tcg_gen_ctzi_i64(ret, ret, 32);
> +}
One nit: use clzi_i64(ret, ret, 64).
Most hosts, including x86_64, naturally return the register width for zero. If
you use something else, like this, then tcg will generate an extra comparison
and conditional move.
In this case you know that zero is impossible, because you just set all of the
high 32 bits, but that knowledge won't be present in the expansion of ctzi.
r~
