The MIPS ISA release 2 is common to 32/64-bit CPUs.
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
target/mips/internal.h | 2 +-
target/mips/mips-defs.h | 6 +-
linux-user/mips/cpu_loop.c | 2 +-
target/mips/cp0_timer.c | 4 +-
target/mips/cpu.c | 2 +-
target/mips/translate.c | 138 ++++++++++++++++++-------------------
6 files changed, 77 insertions(+), 77 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index f71c617a1fe..b14671a9a51 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -361,7 +361,7 @@ static inline void compute_hflags(CPUMIPSState *env)
}
}
- if (env->insn_flags & ISA_MIPS32R2) {
+ if (env->insn_flags & ISA_MIPS_R2) {
if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
env->hflags |= MIPS_HFLAG_COP1X;
}
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 31c02cc20ef..9ef3f517aaa 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -23,7 +23,7 @@
#define ISA_MIPS4 0x0000000000000008ULL
#define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS_R1 0x0000000000000020ULL
-#define ISA_MIPS32R2 0x0000000000000040ULL
+#define ISA_MIPS_R2 0x0000000000000040ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
@@ -76,8 +76,8 @@
#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32)
/* MIPS Technologies "Release 2" */
-#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
-#define CPU_MIPS64R2 (CPU_MIPS64 | ISA_MIPS32R2)
+#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS_R2)
+#define CPU_MIPS64R2 (CPU_MIPS64 | ISA_MIPS_R2)
/* MIPS Technologies "Release 3" */
#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 1e4acf3d6e3..fc5446ade37 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -385,7 +385,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct
target_pt_regs *regs)
prog_req.frdefault &= interp_req.frdefault;
prog_req.fre &= interp_req.fre;
- bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 ||
+ bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 ||
env->insn_flags & ISA_MIPS32R6;
if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c
index 5ec0d6249e9..70de95d338f 100644
--- a/target/mips/cp0_timer.c
+++ b/target/mips/cp0_timer.c
@@ -44,7 +44,7 @@ static void cpu_mips_timer_update(CPUMIPSState *env)
static void cpu_mips_timer_expire(CPUMIPSState *env)
{
cpu_mips_timer_update(env);
- if (env->insn_flags & ISA_MIPS32R2) {
+ if (env->insn_flags & ISA_MIPS_R2) {
env->CP0_Cause |= 1 << CP0Ca_TI;
}
qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
@@ -93,7 +93,7 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value)
if (!(env->CP0_Cause & (1 << CP0Ca_DC))) {
cpu_mips_timer_update(env);
}
- if (env->insn_flags & ISA_MIPS32R2) {
+ if (env->insn_flags & ISA_MIPS_R2) {
env->CP0_Cause &= ~(1 << CP0Ca_TI);
}
qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 112eb0d9f47..5c571434134 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -111,7 +111,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong
val)
uint32_t old = env->CP0_Cause;
int i;
- if (env->insn_flags & ISA_MIPS32R2) {
+ if (env->insn_flags & ISA_MIPS_R2) {
mask |= 1 << CP0Ca_DC;
}
if (env->insn_flags & ISA_MIPS32R6) {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d4e672ebca6..842db4490ce 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7207,7 +7207,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
@@ -7255,27 +7255,27 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
@@ -7291,7 +7291,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case CP0_REGISTER_07:
switch (sel) {
case CP0_REG07__HWRENA:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
break;
@@ -7386,17 +7386,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "Status";
break;
case CP0_REG12__INTCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
case CP0_REG12__SRSMAP:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
break;
@@ -7432,13 +7432,13 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "PRid";
break;
case CP0_REG15__EBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EBase";
break;
case CP0_REG15__CMGCRBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
tcg_gen_ext32s_tl(arg, arg);
@@ -7952,7 +7952,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
ctx->base.is_jmp = DISAS_STOP;
@@ -7998,27 +7998,27 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4";
break;
@@ -8034,7 +8034,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case CP0_REGISTER_07:
switch (sel) {
case CP0_REG07__HWRENA:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "HWREna";
@@ -8117,21 +8117,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "Status";
break;
case CP0_REG12__INTCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
case CP0_REG12__SRSMAP:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
@@ -8176,7 +8176,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "PRid";
break;
case CP0_REG15__EBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
break;
@@ -8715,7 +8715,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
@@ -8760,27 +8760,27 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
@@ -8796,7 +8796,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case CP0_REGISTER_07:
switch (sel) {
case CP0_REG07__HWRENA:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
break;
@@ -8889,17 +8889,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "Status";
break;
case CP0_REG12__INTCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
case CP0_REG12__SRSMAP:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
break;
@@ -8934,12 +8934,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "PRid";
break;
case CP0_REG15__EBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase";
break;
case CP0_REG15__CMGCRBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
register_name = "CMGCRBase";
@@ -9442,7 +9442,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "PageMask";
break;
case CP0_REG05__PAGEGRAIN:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
break;
@@ -9487,27 +9487,27 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "Wired";
break;
case CP0_REG06__SRSCONF0:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0";
break;
case CP0_REG06__SRSCONF1:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1";
break;
case CP0_REG06__SRSCONF2:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2";
break;
case CP0_REG06__SRSCONF3:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3";
break;
case CP0_REG06__SRSCONF4:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4";
break;
@@ -9523,7 +9523,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case CP0_REGISTER_07:
switch (sel) {
case CP0_REG07__HWRENA:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "HWREna";
@@ -9610,21 +9610,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "Status";
break;
case CP0_REG12__INTCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
case CP0_REG12__SRSCTL:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
case CP0_REG12__SRSMAP:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
@@ -9669,7 +9669,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
register_name = "PRid";
break;
case CP0_REG15__EBASE:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
break;
@@ -13048,7 +13048,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int
rd, int sel)
* The Linux kernel will emulate rdhwr if it's not supported natively.
* Therefore only check the ISA in system mode.
*/
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
#endif
t0 = tcg_temp_new();
@@ -15864,12 +15864,12 @@ static void gen_pool32axf(CPUMIPSState *env,
DisasContext *ctx, int rt, int rs)
switch (minor) {
case RDPGPR:
check_cp0_enabled(ctx);
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_load_srsgpr(rs, rt);
break;
case WRPGPR:
check_cp0_enabled(ctx);
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_store_srsgpr(rs, rt);
break;
default:
@@ -24577,7 +24577,7 @@ static void decode_opc_special(CPUMIPSState *env,
DisasContext *ctx)
switch ((ctx->opcode >> 21) & 0x1f) {
case 1:
/* rotr is decoded as srl on non-R2 CPUs */
- if (ctx->insn_flags & ISA_MIPS32R2) {
+ if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_ROTR;
}
/* Fallthrough */
@@ -24603,7 +24603,7 @@ static void decode_opc_special(CPUMIPSState *env,
DisasContext *ctx)
switch ((ctx->opcode >> 6) & 0x1f) {
case 1:
/* rotrv is decoded as srlv on non-R2 CPUs */
- if (ctx->insn_flags & ISA_MIPS32R2) {
+ if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_ROTRV;
}
/* Fallthrough */
@@ -24675,7 +24675,7 @@ static void decode_opc_special(CPUMIPSState *env,
DisasContext *ctx)
switch ((ctx->opcode >> 21) & 0x1f) {
case 1:
/* drotr is decoded as dsrl on non-R2 CPUs */
- if (ctx->insn_flags & ISA_MIPS32R2) {
+ if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_DROTR;
}
/* Fallthrough */
@@ -24693,7 +24693,7 @@ static void decode_opc_special(CPUMIPSState *env,
DisasContext *ctx)
switch ((ctx->opcode >> 21) & 0x1f) {
case 1:
/* drotr32 is decoded as dsrl32 on non-R2 CPUs */
- if (ctx->insn_flags & ISA_MIPS32R2) {
+ if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_DROTR32;
}
/* Fallthrough */
@@ -24725,7 +24725,7 @@ static void decode_opc_special(CPUMIPSState *env,
DisasContext *ctx)
switch ((ctx->opcode >> 6) & 0x1f) {
case 1:
/* drotrv is decoded as dsrlv on non-R2 CPUs */
- if (ctx->insn_flags & ISA_MIPS32R2) {
+ if (ctx->insn_flags & ISA_MIPS_R2) {
op1 = OPC_DROTRV;
}
/* Fallthrough */
@@ -28185,7 +28185,7 @@ static void decode_opc_special3(CPUMIPSState *env,
DisasContext *ctx)
switch (op1) {
case OPC_EXT:
case OPC_INS:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
case OPC_BSHFL:
@@ -28200,7 +28200,7 @@ static void decode_opc_special3(CPUMIPSState *env,
DisasContext *ctx)
decode_opc_special3_r6(env, ctx);
break;
default:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_bshfl(ctx, op2, rt, rd);
break;
}
@@ -28212,7 +28212,7 @@ static void decode_opc_special3(CPUMIPSState *env,
DisasContext *ctx)
case OPC_DINSM:
case OPC_DINSU:
case OPC_DINS:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
@@ -28232,7 +28232,7 @@ static void decode_opc_special3(CPUMIPSState *env,
DisasContext *ctx)
decode_opc_special3_r6(env, ctx);
break;
default:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
check_mips_64(ctx);
op2 = MASK_DBSHFL(ctx->opcode);
gen_bshfl(ctx, op2, rt, rd);
@@ -28359,7 +28359,7 @@ static bool decode_opc_legacy(CPUMIPSState *env,
DisasContext *ctx)
gen_reserved_instruction(ctx);
break;
case OPC_SYNCI:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
/*
* Break the TB to be able to sync copied instructions
* immediately.
@@ -28476,7 +28476,7 @@ static bool decode_opc_legacy(CPUMIPSState *env,
DisasContext *ctx)
}
break;
case OPC_DI:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
save_cpu_state(ctx, 1);
gen_helper_di(t0, cpu_env);
gen_store_gpr(t0, rt);
@@ -28487,7 +28487,7 @@ static bool decode_opc_legacy(CPUMIPSState *env,
DisasContext *ctx)
ctx->base.is_jmp = DISAS_STOP;
break;
case OPC_EI:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
save_cpu_state(ctx, 1);
gen_helper_ei(t0, cpu_env);
gen_store_gpr(t0, rt);
@@ -28508,11 +28508,11 @@ static bool decode_opc_legacy(CPUMIPSState *env,
DisasContext *ctx)
#endif /* !CONFIG_USER_ONLY */
break;
case OPC_RDPGPR:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_load_srsgpr(rt, rd);
break;
case OPC_WRPGPR:
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
gen_store_srsgpr(rt, rd);
break;
default:
@@ -28674,7 +28674,7 @@ static bool decode_opc_legacy(CPUMIPSState *env,
DisasContext *ctx)
case OPC_MFHC1:
case OPC_MTHC1:
check_cp1_enabled(ctx);
- check_insn(ctx, ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS_R2);
/* fall through */
case OPC_MFC1:
case OPC_CFC1:
@@ -28855,21 +28855,21 @@ static bool decode_opc_legacy(CPUMIPSState *env,
DisasContext *ctx)
switch (op1) {
case OPC_LUXC1:
case OPC_SUXC1:
- check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
/* Fallthrough */
case OPC_LWXC1:
case OPC_LDXC1:
case OPC_SWXC1:
case OPC_SDXC1:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
break;
case OPC_PREFX:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
/* Treat as NOP. */
break;
case OPC_ALNV_PS:
- check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
/* Fallthrough */
case OPC_MADD_S:
case OPC_MADD_D:
@@ -28883,7 +28883,7 @@ static bool decode_opc_legacy(CPUMIPSState *env,
DisasContext *ctx)
case OPC_NMSUB_S:
case OPC_NMSUB_D:
case OPC_NMSUB_PS:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
break;
default:
--
2.26.2
