On Tue, Dec 15, 2020 at 4:34 AM Alistair Francis
<alistair.fran...@wdc.com> wrote:
>
> Currently the riscv_is_32_bit() function only supports the generic rv32
> CPUs. Extend the function to support the SiFive and LowRISC CPUs as
> well.
>
> Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
> ---
> hw/riscv/boot.c | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index d62f3dc758..3c70ac75d7 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -41,7 +41,17 @@
>
> bool riscv_is_32_bit(MachineState *machine)
> {
> - if (!strncmp(machine->cpu_type, "rv32", 4)) {
> + /*
> + * To determine if the CPU is 32-bit we need to check a few different
> CPUs.
> + *
> + * If the CPU starts with rv32
> + * If the CPU is a sifive 3 seriries CPU (E31, U34)
> + * If it's the Ibex CPU
> + */
> + if (!strncmp(machine->cpu_type, "rv32", 4) ||
> + (!strncmp(machine->cpu_type, "sifive", 6) &&
> + machine->cpu_type[8] == '3') ||
> + !strncmp(machine->cpu_type, "lowrisc-ibex", 12)) {
This does not look like a scalable way. With more and more CPU added
in the future, this may end up with a huge list of strncmps..
> return true;
> } else {
> return false;
Regards,
Bin
