On 12/8/20 7:43 PM, Maciej W. Rozycki wrote:
> On Tue, 8 Dec 2020, Philippe Mathieu-Daudé wrote:
>
>> Duh I hit that again, read the patch again, looks correct. I guess
>> I got confused myself reviewing the offending patch...
>> So I'm applying this patch to mips-next queue, using
>> Fixes: d9224450208 ("target-mips: Tighten ISA level checks")
>
> What's wrong with current code? What I can see is:
>
> case OPC_LL: /* Load and stores */
> check_insn(ctx, ISA_MIPS2);
> if (ctx->insn_flags & INSN_R5900) {
> check_insn_opc_user_only(ctx, INSN_R5900);
> }
> /* Fallthrough */
> case OPC_LWL:
> case OPC_LWR:
> check_insn_opc_removed(ctx, ISA_MIPS32R6);
> /* Fallthrough */
> case OPC_LB:
> case OPC_LH:
> case OPC_LW:
> case OPC_LWPC:
> case OPC_LBU:
> case OPC_LHU:
> gen_ld(ctx, op, rt, rs, imm);
> break;
>
> which looks absolutely right to me: LL is accepted with MIPS2--MIPS32R5
> (including R5900 in user emulation only), LWL/LWR are accepted with
> MIPS1--MIPS32R5 and the remaining loads are accepted everywhere. What
> else do you need?
I am clearly bleary-eyed... Sorry. Patch dropped.
