On 11/19/20 3:56 PM, Peter Maydell wrote: > For v8.1M the architecture mandates that CPUs must provide at > least the "minimal RAS implementation" from the Reliability, > Availability and Serviceability extension. This consists of: > * an ESB instruction which is a NOP > -- since it is in the HINT space we need only add a comment > * an RFSR register which will RAZ/WI > * a RAZ/WI AIRCR.IESB bit > -- the code which handles writes to AIRCR does not allow setting > of RES0 bits, so we already treat this as RAZ/WI; add a comment > noting that this is deliberate > * minimal implementation of the RAS register block at 0xe0005000 > -- this will be in a subsequent commit > * setting the ID_PFR0.RAS field to 0b0010 > -- we will do this when we add the Cortex-M55 CPU model > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/arm/cpu.h | 14 ++++++++++++++ > target/arm/t32.decode | 4 ++++ > hw/intc/armv7m_nvic.c | 13 +++++++++++++ > 3 files changed, 31 insertions(+)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
