On Monday, November 30, 2020 1:40 AM, Peter Maydell wrote: > The Nios2 architecture supports two different interrupt controller > options: > > * The IIC (Internal Interrupt Controller) is part of the CPU itself; > it has 32 IRQ input lines and no NMI support. Interrupt status is > queried and controlled via the CPU's ipending and istatus > registers. > > * The EIC (External Interrupt Controller) interface allows the CPU > to connect to an external interrupt controller. The interface > allows the interrupt controller to present a packet of information > containing: > - handler address > - interrupt level > - register set > - NMI mode > > QEMU does not model an EIC currently. We do model the IIC, but its > implementation is split across code in hw/nios2/cpu_pic.c and > hw/intc/nios2_iic.c. The code in those two files has no state of its own -- > the IIC > state is in the Nios2CPU state struct. > > Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they can have > GPIO input lines themselves, so we can implement the IIC directly in the CPU > object the same way that real hardware does. > > Create named "IRQ" GPIO inputs to the Nios2 CPU object, and make the only > user of the IIC wire up directly to those instead. > > Note that the old code had an "NMI" concept which was entirely unused and > also as far as I can see not architecturally correct, since only the EIC has a > concept of an NMI. > > This fixes a Coverity-reported trivial memory leak of the IRQ array allocated > in > nios2_cpu_pic_init(). > > Fixes: Coverity CID 1421916 > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/nios2/cpu.h | 1 - > hw/intc/nios2_iic.c | 95 --------------------------------------- > hw/nios2/10m50_devboard.c | 13 +----- > hw/nios2/cpu_pic.c | 31 ------------- > target/nios2/cpu.c | 30 +++++++++++++ > MAINTAINERS | 1 - > hw/intc/meson.build | 1 - > 7 files changed, 32 insertions(+), 140 deletions(-) delete mode 100644 > hw/intc/nios2_iic.c
Reviewed and tested.
