From: Frank Chang <frank.ch...@sifive.com> This patchset implements RISC-V B-extension latest draft version (2020.10.26) Zbb, Zbs and Zba subset instructions.
Specification: https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf The port is available here: https://github.com/sifive/qemu/tree/rvb-upstream-v1 To test rvb implementation, specify cpu argument with 'x-b=true' to enable B-extension support. Frank Chang (2): target/riscv: rvb: generalized reverse target/riscv: rvb: generalized or-combine Kito Cheng (13): target/riscv: reformat @sh format encoding for B-extension target/riscv: rvb: count leading/trailing zeros target/riscv: rvb: count bits set target/riscv: rvb: logic-with-negate target/riscv: rvb: pack two words into one register target/riscv: rvb: min/max instructions target/riscv: rvb: sign-extend instructions target/riscv: rvb: single-bit instructions target/riscv: rvb: shift ones target/riscv: rvb: rotate (left/right) target/riscv: rvb: address calculation target/riscv: rvb: add/sub with postfix zero-extend target/riscv: rvb: support and turn on B-extension from command line target/riscv/bitmanip_helper.c | 128 +++++ target/riscv/cpu.c | 4 + target/riscv/cpu.h | 2 + target/riscv/helper.h | 9 + target/riscv/insn32-64.decode | 37 ++ target/riscv/insn32.decode | 54 ++- target/riscv/insn_trans/trans_rvb.c.inc | 475 +++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 597 ++++++++++++++++++++++++ 9 files changed, 1301 insertions(+), 6 deletions(-) create mode 100644 target/riscv/bitmanip_helper.c create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc -- 2.17.1
