Hi Mateja,
(Cc'ing Fredrik)
On 2/27/19 3:00 PM, Aleksandar Markovic wrote:
> From: Mateja Marjanovic <mateja.marjano...@rt-rk.com>
>
> Set up MMI code to be compiled only for TARGET_MIPS64. This is
> needed so that GPRs are 64 bit, and combined with MMI registers,
> they will form full 128 bit registers.
>
> Signed-off-by: Mateja Marjanovic <mateja.marjano...@rt-rk.com>
> Signed-off-by: Aleksandar Markovic <amarko...@wavecomp.com>
> Reviewed-by: Aleksandar Rikalo <arik...@wavecomp.com>
> Message-Id: <1551183797-13570-2-git-send-email-mateja.marjano...@rt-rk.com>
> ---
> target/mips/translate.c | 43 +++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 41 insertions(+), 2 deletions(-)
...
> static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
> {
> int rs, rt, rd, sa;
> @@ -28796,10 +28828,11 @@ static void decode_opc(CPUMIPSState *env,
> DisasContext *ctx)
> decode_opc_special(env, ctx);
> break;
> case OPC_SPECIAL2:
> +#if defined(TARGET_MIPS64)
> if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
> decode_mmi(env, ctx);
This change is incorrect, you removed support for the
MADD[U] and MULT[U] instructions on TXx9 32-bit targets
(TX79 still works).
> -#if !defined(TARGET_MIPS64)
> - } else if (ctx->insn_flags & ASE_MXU) {
> +#else
> + if (ctx->insn_flags & ASE_MXU) {
> decode_opc_mxu(env, ctx);
> #endif
...
