On Tue, Nov 10, 2020 at 6:50 AM Vitaly Wool <vitaly.w...@konsulko.com> wrote:
>
> Add QSPI NOR flash definition for Microchip PolarFire SoC.
>
> Signed-off-by: Vitaly Wool <vitaly.w...@konsulko.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> hw/riscv/microchip_pfsoc.c | 21 +++++++++++++++++++++
> include/hw/riscv/microchip_pfsoc.h | 3 +++
> 2 files changed, 24 insertions(+)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 4627179cd3..d1f4a1fe6f 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -90,6 +90,8 @@ static const struct MemmapEntry {
> [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
> [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
> [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
> + [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 },
> + [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 },
> [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
> [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
> [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
> @@ -97,6 +99,7 @@ static const struct MemmapEntry {
> [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
> + [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
> [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
> [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
> };
> @@ -147,6 +150,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
> Error **errp)
> MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
> MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> MemoryRegion *envm_data = g_new(MemoryRegion, 1);
> + MemoryRegion *xip_mem = g_new(MemoryRegion, 1);
> char *plic_hart_config;
> size_t plic_hart_config_len;
> NICInfo *nd;
> @@ -302,6 +306,15 @@ static void microchip_pfsoc_soc_realize(DeviceState
> *dev, Error **errp)
> qdev_set_nic_properties(DEVICE(&s->gem1), nd);
> }
>
> + /* SPI */
> + create_unimplemented_device("microchip.pfsoc.spi0",
> + memmap[MICROCHIP_PFSOC_SPI0].base,
> + memmap[MICROCHIP_PFSOC_SPI0].size);
> +
> + create_unimplemented_device("microchip.pfsoc.spi1",
> + memmap[MICROCHIP_PFSOC_SPI1].base,
> + memmap[MICROCHIP_PFSOC_SPI1].size);
> +
> object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION,
> errp);
> object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
> sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
> @@ -337,6 +350,14 @@ static void microchip_pfsoc_soc_realize(DeviceState
> *dev, Error **errp)
> memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
> envm_data);
>
> + /* QSPI Flash */
> + memory_region_init_rom(xip_mem, OBJECT(dev), "microchip.pfsoc.xip",
> + memmap[MICROCHIP_PFSOC_QSPI_XIP].size,
> + &error_fatal);
> + memory_region_add_subregion(system_memory,
> + memmap[MICROCHIP_PFSOC_QSPI_XIP].base,
> + xip_mem);
> +
> /* IOSCBCFG */
> create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
> memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
> diff --git a/include/hw/riscv/microchip_pfsoc.h
> b/include/hw/riscv/microchip_pfsoc.h
> index 8bfc7e1a85..28d6f389ec 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -87,6 +87,8 @@ enum {
> MICROCHIP_PFSOC_MMUART2,
> MICROCHIP_PFSOC_MMUART3,
> MICROCHIP_PFSOC_MMUART4,
> + MICROCHIP_PFSOC_SPI0,
> + MICROCHIP_PFSOC_SPI1,
> MICROCHIP_PFSOC_GEM0,
> MICROCHIP_PFSOC_GEM1,
> MICROCHIP_PFSOC_GPIO0,
> @@ -94,6 +96,7 @@ enum {
> MICROCHIP_PFSOC_GPIO2,
> MICROCHIP_PFSOC_ENVM_CFG,
> MICROCHIP_PFSOC_ENVM_DATA,
> + MICROCHIP_PFSOC_QSPI_XIP,
> MICROCHIP_PFSOC_IOSCB_CFG,
> MICROCHIP_PFSOC_DRAM,
> };
> --
> 2.20.1
>
>
