On Fri, Oct 23, 2020 at 12:13 PM Richard Henderson <richard.hender...@linaro.org> wrote: > > On 10/23/20 8:26 AM, Alistair Francis wrote: > > +++ b/target/riscv/cpu-param.h > > @@ -18,6 +18,6 @@ > > # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ > > #endif > > #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ > > -#define NB_MMU_MODES 4 > > +#define NB_MMU_MODES 8 > > Is there really a PRV_M + virt enabled state?
No, there isn't. > > > +#define TB_FLAGS_PRIV_MMU_MASK 3 > ... > > - int mode = mmu_idx; > > + int mode = mmu_idx & 0x3; > > Use that MASK here? Good idea. Alistair > > > r~
