Allow the get_field() and set_field() macros to work on 64-bit values even on 32-bit RISC-V.
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/cpu_bits.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index d9ad694b3f..db46739b1c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -4,10 +4,10 @@ #define TARGET_RISCV_CPU_BITS_H #define get_field(reg, mask) (((reg) & \ - (target_ulong)(mask)) / ((mask) & ~((mask) << 1))) -#define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \ - (((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \ - (target_ulong)(mask))) + (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) +#define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \ + (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \ + (uint64_t)(mask))) /* Floating point round mode */ #define FSR_RD_SHIFT 5 -- 2.28.0
