We sometime get kernel panic with some devices on Aarch64
hosts. Alex Williamson suggests it might be broken PCIe
root complex. Add trace event to record the latest I/O
access before crashing. In case, assert our accesses are
aligned.
Reviewed-by: Fam Zheng <f...@euphon.net>
Signed-off-by: Philippe Mathieu-Daudé <phi...@redhat.com>
---
util/vfio-helpers.c | 8 ++++++++
util/trace-events | 2 ++
2 files changed, 10 insertions(+)
diff --git a/util/vfio-helpers.c b/util/vfio-helpers.c
index bce2cdb2f3c..ac9cc20ce29 100644
--- a/util/vfio-helpers.c
+++ b/util/vfio-helpers.c
@@ -228,6 +228,10 @@ static int qemu_vfio_pci_read_config(QEMUVFIOState *s,
void *buf,
{
int ret;
+ trace_qemu_vfio_pci_read_config(buf, ofs, size,
+ s->config_region_info.offset,
+ s->config_region_info.size);
+ assert(QEMU_IS_ALIGNED(s->config_region_info.offset + ofs, size));
do {
ret = pread(s->device, buf, size, s->config_region_info.offset + ofs);
} while (ret == -1 && errno == EINTR);
@@ -238,6 +242,10 @@ static int qemu_vfio_pci_write_config(QEMUVFIOState *s,
void *buf, int size, int
{
int ret;
+ trace_qemu_vfio_pci_write_config(buf, ofs, size,
+ s->config_region_info.offset,
+ s->config_region_info.size);
+ assert(QEMU_IS_ALIGNED(s->config_region_info.offset + ofs, size));
do {
ret = pwrite(s->device, buf, size, s->config_region_info.offset + ofs);
} while (ret == -1 && errno == EINTR);
diff --git a/util/trace-events b/util/trace-events
index 19f03f14a33..b697d2d5429 100644
--- a/util/trace-events
+++ b/util/trace-events
@@ -86,3 +86,5 @@ qemu_vfio_do_mapping(void *s, void *host, size_t size,
uint64_t iova) "s %p host
qemu_vfio_dma_map(void *s, void *host, size_t size, bool temporary, uint64_t
*iova) "s %p host %p size 0x%zx temporary %d iova %p"
qemu_vfio_dma_unmap(void *s, void *host) "s %p host %p"
qemu_vfio_iommu_iova_pgsizes(uint64_t iova_pgsizes) "iommu page size bitmask:
0x%08"PRIx64
+qemu_vfio_pci_read_config(void *buf, int ofs, int size, uint64_t region_ofs,
uint64_t region_size) "read cfg ptr %p ofs 0x%x size %d (region ofs 0x%"PRIx64"
size %"PRId64")"
+qemu_vfio_pci_write_config(void *buf, int ofs, int size, uint64_t region_ofs,
uint64_t region_size) "write cfg ptr %p ofs 0x%x size %d (region ofs
0x%"PRIx64" size %"PRId64")"
--
2.26.2
