On Wed, Oct 07, 2020 at 12:24:32PM +0200, Philippe Mathieu-Daudé wrote:
> On 10/7/20 12:07 PM, Graeme Gregory wrote:
> > SMMUv3 has an error in a previous patch where an i was transposed to a 1
> > meaning interrupts would not have been correctly assigned to the SMMUv3
> > instance.
> >
> > Fixes: 48ba18e6d3f3 ("hw/arm/sbsa-ref: Simplify by moving the gic in the
> > machine state")
> > Signed-off-by: Graeme Gregory <gra...@nuviainc.com>
>
> Again, this fix is already in Peter's queue:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg732819.html
>
> But if you repost, please collect the reviewer tags,
> so we don't have to review it again. This one has:
> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
> Reviewed-by: Eric Auger <eric.au...@redhat.com>
>
Ah I thought splitting the patch invalidated Eric's reviewed by?
This is a different fix to the one you are referring to, previous one
was in PCIe.
Apologies if I have missed an email from you but I have not received a
Reviewed by from you for the SMMUv3 IRQ fix.
Thanks
Graeme
> Thanks,
>
> Phil.
>
> > ---
> > hw/arm/sbsa-ref.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
> > index 9c3a893bed..65e64883b5 100644
> > --- a/hw/arm/sbsa-ref.c
> > +++ b/hw/arm/sbsa-ref.c
> > @@ -525,7 +525,7 @@ static void create_smmu(const SBSAMachineState *sms,
> > PCIBus *bus)
> > sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
> > for (i = 0; i < NUM_SMMU_IRQS; i++) {
> > sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
> > - qdev_get_gpio_in(sms->gic, irq + 1));
> > + qdev_get_gpio_in(sms->gic, irq + i));
> > }
> > }
> >
> >
