On 9/28/20 9:03 PM, Yifei Jiang wrote: > In the case of supporting V extention, add V extention description > to vmstate_riscv_cpu. > > Signed-off-by: Yifei Jiang <jiangyi...@huawei.com> > Signed-off-by: Yipeng Yin <yinyipe...@huawei.com> > --- > target/riscv/machine.c | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Though of course this is racing with the v1.0 patch set, which changes the set of vector csrs. r~
