The following changes since commit 9435a8b3dd35f1f926f1b9127e8a906217a5518a:
Merge remote-tracking branch
'remotes/kraxel/tags/sirius/ipxe-20200908-pull-request' into staging
(2020-09-08 21:21:13 +0100)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200910
for you to fetch changes up to 7595a65818ea9b49c36650a8c217a1ef9bd6e62a:
hw/riscv: Sort the Kconfig options in alphabetical order (2020-09-09 15:54:19
-0700)
----------------------------------------------------------------
This PR includes multiple fixes and features for RISC-V:
- Fixes a bug in printing trap causes
- Allows 16-bit writes to the SiFive test device. This fixes the
failure to reboot the RISC-V virt machine
- Support for the Microchip PolarFire SoC and Icicle Kit
- A reafactor of RISC-V code out of hw/riscv
----------------------------------------------------------------
Bin Meng (28):
target/riscv: cpu: Add a new 'resetvec' property
hw/riscv: hart: Add a new 'resetvec' property
target/riscv: cpu: Set reset vector based on the configured property value
hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
hw/char: Add Microchip PolarFire SoC MMUART emulation
hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
hw/sd: Add Cadence SDHCI emulation
hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD
card
hw/dma: Add SiFive platform DMA controller emulation
hw/riscv: microchip_pfsoc: Connect a DMA controller
hw/net: cadence_gem: Add a new 'phy-addr' property
hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
hw/riscv: microchip_pfsoc: Hook GPIO controllers
hw/riscv: clint: Avoid using hard-coded timebase frequency
hw/riscv: sifive_u: Connect a DMA controller
hw/riscv: Move sifive_e_prci model to hw/misc
hw/riscv: Move sifive_u_prci model to hw/misc
hw/riscv: Move sifive_u_otp model to hw/misc
hw/riscv: Move sifive_gpio model to hw/gpio
hw/riscv: Move sifive_clint model to hw/intc
hw/riscv: Move sifive_plic model to hw/intc
hw/riscv: Move riscv_htif model to hw/char
hw/riscv: Move sifive_uart model to hw/char
hw/riscv: Move sifive_test model to hw/misc
hw/riscv: Always build riscv_hart.c
hw/riscv: Drop CONFIG_SIFIVE
hw/riscv: Sort the Kconfig options in alphabetical order
Nathan Chancellor (1):
riscv: sifive_test: Allow 16-bit writes to memory region
Yifei Jiang (1):
target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
default-configs/riscv64-softmmu.mak | 1 +
{include/hw/riscv => hw/intc}/sifive_plic.h | 0
hw/riscv/trace.h | 1 -
include/hw/char/mchp_pfsoc_mmuart.h | 61 ++++
include/hw/{riscv => char}/riscv_htif.h | 0
include/hw/{riscv => char}/sifive_uart.h | 0
include/hw/dma/sifive_pdma.h | 57 ++++
include/hw/{riscv => gpio}/sifive_gpio.h | 0
include/hw/{riscv => intc}/sifive_clint.h | 4 +-
include/hw/{riscv => misc}/sifive_e_prci.h | 0
include/hw/{riscv => misc}/sifive_test.h | 0
include/hw/{riscv => misc}/sifive_u_otp.h | 0
include/hw/{riscv => misc}/sifive_u_prci.h | 0
include/hw/net/cadence_gem.h | 2 +
include/hw/riscv/microchip_pfsoc.h | 133 +++++++++
include/hw/riscv/riscv_hart.h | 1 +
include/hw/riscv/sifive_e.h | 2 +-
include/hw/riscv/sifive_u.h | 17 +-
include/hw/sd/cadence_sdhci.h | 47 +++
target/riscv/cpu.h | 8 +-
hw/arm/xilinx_zynq.c | 1 +
hw/arm/xlnx-versal.c | 1 +
hw/arm/xlnx-zynqmp.c | 2 +
hw/char/mchp_pfsoc_mmuart.c | 86 ++++++
hw/{riscv => char}/riscv_htif.c | 2 +-
hw/{riscv => char}/sifive_uart.c | 2 +-
hw/dma/sifive_pdma.c | 313 ++++++++++++++++++++
hw/{riscv => gpio}/sifive_gpio.c | 2 +-
hw/{riscv => intc}/sifive_clint.c | 28 +-
hw/{riscv => intc}/sifive_plic.c | 2 +-
hw/{riscv => misc}/sifive_e_prci.c | 2 +-
hw/{riscv => misc}/sifive_test.c | 4 +-
hw/{riscv => misc}/sifive_u_otp.c | 2 +-
hw/{riscv => misc}/sifive_u_prci.c | 2 +-
hw/net/cadence_gem.c | 7 +-
hw/riscv/microchip_pfsoc.c | 437 ++++++++++++++++++++++++++++
hw/riscv/opentitan.c | 1 +
hw/riscv/riscv_hart.c | 3 +
hw/riscv/sifive_e.c | 12 +-
hw/riscv/sifive_u.c | 41 ++-
hw/riscv/spike.c | 7 +-
hw/riscv/virt.c | 9 +-
hw/sd/cadence_sdhci.c | 193 ++++++++++++
target/riscv/cpu.c | 19 +-
target/riscv/cpu_helper.c | 8 +-
target/riscv/csr.c | 4 +-
MAINTAINERS | 9 +
hw/char/Kconfig | 9 +
hw/char/meson.build | 3 +
hw/dma/Kconfig | 3 +
hw/dma/meson.build | 1 +
hw/gpio/Kconfig | 3 +
hw/gpio/meson.build | 1 +
hw/gpio/trace-events | 6 +
hw/intc/Kconfig | 6 +
hw/intc/meson.build | 2 +
hw/misc/Kconfig | 12 +
hw/misc/meson.build | 6 +
hw/riscv/Kconfig | 70 +++--
hw/riscv/meson.build | 12 +-
hw/riscv/trace-events | 7 -
hw/sd/Kconfig | 4 +
hw/sd/meson.build | 1 +
meson.build | 1 -
64 files changed, 1575 insertions(+), 105 deletions(-)
rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
delete mode 100644 hw/riscv/trace.h
create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
rename include/hw/{riscv => char}/riscv_htif.h (100%)
rename include/hw/{riscv => char}/sifive_uart.h (100%)
create mode 100644 include/hw/dma/sifive_pdma.h
rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
rename include/hw/{riscv => intc}/sifive_clint.h (92%)
rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
rename include/hw/{riscv => misc}/sifive_test.h (100%)
rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
create mode 100644 include/hw/riscv/microchip_pfsoc.h
create mode 100644 include/hw/sd/cadence_sdhci.h
create mode 100644 hw/char/mchp_pfsoc_mmuart.c
rename hw/{riscv => char}/riscv_htif.c (99%)
rename hw/{riscv => char}/sifive_uart.c (99%)
create mode 100644 hw/dma/sifive_pdma.c
rename hw/{riscv => gpio}/sifive_gpio.c (99%)
rename hw/{riscv => intc}/sifive_clint.c (90%)
rename hw/{riscv => intc}/sifive_plic.c (99%)
rename hw/{riscv => misc}/sifive_e_prci.c (99%)
rename hw/{riscv => misc}/sifive_test.c (97%)
rename hw/{riscv => misc}/sifive_u_otp.c (99%)
rename hw/{riscv => misc}/sifive_u_prci.c (99%)
create mode 100644 hw/riscv/microchip_pfsoc.c
create mode 100644 hw/sd/cadence_sdhci.c
delete mode 100644 hw/riscv/trace-events
