From: Eric Auger <eric.au...@redhat.com>
The SMMU IIDR register is at 0x018 offset.
Fixes: 10a83cb9887 ("hw/arm/smmuv3: Skeleton")
Signed-off-by: Eric Auger <eric.au...@redhat.com>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 20200728150815.11446-9-eric.au...@redhat.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
hw/arm/smmuv3-internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 5babf72f7d5..ef093eaff50 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -63,7 +63,7 @@ REG32(IDR5, 0x14)
#define SMMU_IDR5_OAS 4
-REG32(IIDR, 0x1c)
+REG32(IIDR, 0x18)
REG32(CR0, 0x20)
FIELD(CR0, SMMU_ENABLE, 0, 1)
FIELD(CR0, EVENTQEN, 2, 1)
--
2.20.1
