Hi Philippe, On Fri, Aug 21, 2020 at 10:21 PM Philippe Mathieu-Daudé <f4...@amsat.org> wrote: > > Hi Bin, > > On 8/21/20 2:54 AM, Bin Meng wrote: > > Hi Philippe, > > > > On Fri, Aug 21, 2020 at 2:04 AM Philippe Mathieu-Daudé <f4...@amsat.org> > > wrote: > >> > >> Hi Sai Pavan, you said you were interested to test the first 2 > >> patches. FYI I plan to queue them and send the pull request tomorrow > >> or Saturday the latest. > > > > Have you got a chance to review the v2 of 3rd patch? > > > > "hw/sd: Add Cadence SDHCI emulation" > > I'll have a look at it, but it makes sense to merge it via the > tree using it (so the RISCV tree).
Thank you. Sure I will include the Cadence SDHCI patch in the PolarFire SoC support series in the next version. > > Meanwhile I'm queueing patches 1 and 2 to my sd-next tree, > adding the Tested-by from Sai Pavan from: > https://www.mail-archive.com/qemu-devel@nongnu.org/msg732027.html > I just noticed that the v2 patch has the wrong author email address, so I plan to send v3 of patch 1 and 2 to correct it, with Sai Pavan's Tested-by tag. Sorry! Regards, Bin
