Hi Anup, On Sat, Aug 15, 2020 at 1:44 AM Anup Patel <a...@brainfault.org> wrote: > > On Fri, Aug 14, 2020 at 10:12 PM Bin Meng <bmeng...@gmail.com> wrote: > > > > From: Bin Meng <bin.m...@windriver.com> > > > > This adds support for Microchip PolarFire SoC Icicle Kit board. > > The Icicle Kit board integrates a PolarFire SoC, with one SiFive's > > E51 plus four U54 cores and many on-chip peripherals and an FPGA. > > Nice Work !!! This is very helpful.
Thanks! > > > > > For more details about Microchip PolarFire Soc, please see: > > https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga > > > > The Icicle Kit board information can be found here: > > https://www.microsemi.com/existing-parts/parts/152514 > > > > Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000. > > The RISC-V CPU and HART codes has been updated to set the core's > > reset vector based on a configurable property from machine codes. > > > > The following perepherals are created as an unimplemented device: > > > > - Bus Error Uint 0/1/2/3/4 > > - L2 cache controller > > - SYSREG > > - MPUCFG > > - IOSCBCFG > > - GPIO > > > > The following perepherals are emulated: > > - SiFive CLINT > > - SiFive PLIC > > - PolarFire SoC Multi-Mode UART > > - PolarFire SoC DMA > > - Cadence eMMC/SDHCI controller > > - Cadence Gigabit Ethernet MAC > > > > Some bugs in the SD card codes are fixed during the development. > > > > The BIOS image used by this machine is hss.bin, aka Hart Software > > Services, which can be built from: > > https://github.com/polarfire-soc/hart-software-services > > > > To launch this machine: > > $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \ > > -bios path/to/hss.bin -sd path/to/sdcard.img \ > > -nic tap,ifname=tap,script=no,model=cadence_gem \ > > -display none -serial stdio \ > > -chardev socket,id=serial1,path=serial1.sock,server,wait \ > > -serial chardev:serial1 > > Currently, it is fine to use HSS (with OpenSBI v0.6 as a library) but > this is not aligned with the existing booting flow of many RISC-V > systems. Yep, unfortunately this is the case currently. > > It will be nice to have standard U-Boot RISC-V boot-flow working > on Microchip PolarFire SoC: > U-Boot SPL (BIOS) => FW_DYNAMIC (Generic) => U-Boot S-mode > Agreed. > The Microchip HSS is quite convoluted. It has: > 1. DDR Init > 2. Boot device support > 3. SBI support using OpenSBI as library > 4. Simple TEE support > > I think point 1) and 2) above should be part of U-Boot SPL. > The point 3) can be OpenSBI FW_DYNAMIC. > > Lastly,for point 4), we are working on a new OpenSBI feature using > which we can run independent Secure OS and Non-Secure OS using > U-Boot_SPL+OpenSBI (for both SiFive Unleashed and Microchip > PolarFire). > > Do you have plans for adding U-Boot SPL support for this board ?? + Cyril Jean from Microchip I will have to leave this question to Cyril to comment. Regards, Bin
