On Sat, Jul 25, 2020 at 8:04 AM Zong Li <zong...@sifive.com> wrote:
>
> On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp
> entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original
> implementation, the second parameter of pmp_write_cfg is
> "reg_index * sizeof(target_ulong)", and we get the the result
> which is started from 16 if reg_index is 2, but we expect that
> it should be started from 8. Separate the implementation for
> RV32 and RV64 respectively.
>
> Signed-off-by: Zong Li <zong...@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/pmp.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 2a2b9f5363..aeba796484 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -318,6 +318,10 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t
> reg_index,
> return;
> }
>
> +#if defined(TARGET_RISCV64)
> + reg_index >>= 1;
> +#endif
> +
> for (i = 0; i < sizeof(target_ulong); i++) {
> cfg_val = (val >> 8 * i) & 0xff;
> pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i,
> @@ -335,11 +339,16 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env,
> uint32_t reg_index)
> target_ulong cfg_val = 0;
> target_ulong val = 0;
>
> + trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val);
> +
> +#if defined(TARGET_RISCV64)
> + reg_index >>= 1;
> +#endif
> +
> for (i = 0; i < sizeof(target_ulong); i++) {
> val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);
> cfg_val |= (val << (i * 8));
> }
> - trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val);
>
> return cfg_val;
> }
> --
> 2.27.0
>
>
