On 7/10/20 3:48 AM, frank.ch...@sifive.com wrote:
> -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
> +static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a)
Do not mix this change with anything else.
> + rd = tcg_const_i32(a->rd);
> + rs1 = tcg_const_i32(a->rs1);
Any time you put a register number into a tcg const, there's probably a better
way to do things.
> - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
> - if (a->rs1 == 0) {
> - /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> - s1 = tcg_const_tl(RV_VLEN_MAX);
> - } else {
> - s1 = tcg_temp_new();
> - gen_get_gpr(s1, a->rs1);
> - }
E.g. this code should be kept, and add
if (a->rd == 0 && a->rs1 == 0) {
s1 = tcg_temp_new();
tcg_gen_mov_tl(s1, cpu_vl);
} else ...
> + if ((sew > cpu->cfg.elen)
> + || vill
> + || vflmul < ((float)sew / cpu->cfg.elen)
> + || (ediv != 0)
> + || (reserved != 0)) {
> /* only set vill bit. */
> env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
> - env->vl = 0;
> - env->vstart = 0;
> return 0;
> }
You do need to check 0.7.1 so long as it's supported.
r~
