From: Michael Rolnik <mrol...@gmail.com>
Initialize TCG register variables.
Co-developed-by: Richard Henderson <richard.hender...@linaro.org>
Co-developed-by: Michael Rolnik <mrol...@gmail.com>
Signed-off-by: Michael Rolnik <mrol...@gmail.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.m...@gmail.com>
Tested-by: Philippe Mathieu-Daudé <phi...@redhat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.m...@gmail.com>
Signed-off-by: Thomas Huth <h...@tuxfamily.org>
Message-Id: <20200705140315.260514-18-h...@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
target/avr/translate.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 7ad3dec031..3d8a77e5ae 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -128,6 +128,35 @@ struct DisasContext {
bool free_skip_var0;
};
+void avr_cpu_tcg_init(void)
+{
+ int i;
+
+#define AVR_REG_OFFS(x) offsetof(CPUAVRState, x)
+ cpu_pc = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc");
+ cpu_Cf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf");
+ cpu_Zf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf");
+ cpu_Nf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf");
+ cpu_Vf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf");
+ cpu_Sf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf");
+ cpu_Hf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf");
+ cpu_Tf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf");
+ cpu_If = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If");
+ cpu_rampD = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "rampD");
+ cpu_rampX = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "rampX");
+ cpu_rampY = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "rampY");
+ cpu_rampZ = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "rampZ");
+ cpu_eind = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind");
+ cpu_sp = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp");
+ cpu_skip = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip");
+
+ for (i = 0; i < NUMBER_OF_CPU_REGISTERS; i++) {
+ cpu_r[i] = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]),
+ reg_names[i]);
+ }
+#undef AVR_REG_OFFS
+}
+
static int to_regs_16_31_by_one(DisasContext *ctx, int indx)
{
return 16 + (indx % 16);
--
2.21.3
