On Wed, Jul 1, 2020 at 11:40 AM Atish Patra <atish.pa...@wdc.com> wrote: > > This series adds support OpenSBI dynamic firmware support to Qemu. > Qemu loader passes the information about the DT and next stage (i.e. kernel > or U-boot) via "a2" register. It allows the user to build bigger OS images > without worrying about overwriting DT. It also unifies the reset vector code > in rom and dt placement. Now, the DT is copied directly in DRAM instead of > ROM. > > The changes have been verified on following qemu machines. > > 64bit: > - spike, sifive_u, virt > 32bit: > - virt > > I have also verified fw_jump on all the above platforms to ensure that this > series doesn't break the existing setup. > > Changes from v3->v4: > 1. Addressed all review comments. > 2. Added another patch that allows to boot a qemu machine from 64bit > start address for RV64. > > Changes from v2->v3: > 1. Removed redundant header includes. > > Changes from v1->v2: > 1. Rebased on top of latest upstream Qemu (with MSEL changes for sifive_u). > 2. Improved the code organization > > Atish Patra (4): > riscv: Unify Qemu's reset vector code path > RISC-V: Copy the fdt in dram instead of ROM > riscv: Add opensbi firmware dynamic support > RISC-V: Support 64 bit start address
Thanks! Applied to riscv-to-apply.next Alistair > > hw/riscv/boot.c | 107 ++++++++++++++++++++++++++++++++ > hw/riscv/sifive_u.c | 51 +++++++++------ > hw/riscv/spike.c | 57 +++++------------ > hw/riscv/virt.c | 55 +++++----------- > include/hw/riscv/boot.h | 7 +++ > include/hw/riscv/boot_opensbi.h | 58 +++++++++++++++++ > 6 files changed, 236 insertions(+), 99 deletions(-) > create mode 100644 include/hw/riscv/boot_opensbi.h > > -- > 2.26.2 > >
