On Fri, 26 Jun 2020 at 16:15, Peter Maydell <peter.mayd...@linaro.org> wrote:
>
> From: Richard Henderson <richard.hender...@linaro.org>
>
> Because the elements are non-sequential, we cannot eliminate many
> tests straight away like we can for sequential operations. But
> we often have the PTE details handy, so we can test for Tagged.
>
> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> Message-id: 20200626033144.790098-38-richard.hender...@linaro.org
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Hi; Coverity points out that something went wrong here
(CID 1429996):
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -5261,7 +5261,7 @@ static bool trans_ST_zpri(DisasContext *s,
> arg_rpri_store *a)
> */
>
> static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
> - int scale, TCGv_i64 scalar, int msz,
> + int scale, TCGv_i64 scalar, int msz, bool is_write,
> gen_helper_gvec_mem_scatter *fn)
> {
> unsigned vsz = vec_full_reg_size(s);
> @@ -5269,8 +5269,16 @@ static void do_mem_zpz(DisasContext *s, int zt, int
> pg, int zm,
> TCGv_ptr t_pg = tcg_temp_new_ptr();
> TCGv_ptr t_zt = tcg_temp_new_ptr();
> TCGv_i32 t_desc;
> - int desc;
> + int desc = 0;
>
> + if (s->mte_active[0]) {
> + desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
> + desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
> + desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
> + desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
> + desc = FIELD_DP32(desc, MTEDESC, ESIZE, 1 << msz);
> + desc <<= SVE_MTEDESC_SHIFT;
We carefully set up desc here...
> + }
> desc = simd_desc(vsz, vsz, scale);
...but immediately overwrite it. Should desc have been an input here somewhere?
> t_desc = tcg_const_i32(desc);
thanks
-- PMM
