On Fri, Jun 19, 2020 at 5:37 AM Peter Maydell <peter.mayd...@linaro.org> wrote:
>
> On Fri, 19 Jun 2020 at 07:34, Alistair Francis <alistair.fran...@wdc.com>
> wrote:
> >
> > The following changes since commit eefe34ea4b82c2b47abe28af4cc7247d51553626:
> >
> > Merge remote-tracking branch
> > 'remotes/dgilbert/tags/pull-migration-20200617a' into staging (2020-06-18
> > 15:30:13 +0100)
> >
> > are available in the Git repository at:
> >
> > g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200618-1
> >
> > for you to fetch changes up to fad6a8463510ff5e0fb31bb451a6c3218a45d179:
> >
> > hw/riscv: sifive_u: Add a dummy DDR memory controller device (2020-06-18
> > 23:09:16 -0700)
> >
> > ----------------------------------------------------------------
> > This is a range of patches for RISC-V.
> >
> > Some key points are:
> > - Generalise the CPU init functions
> > - Support the SiFive revB machine
> > - Improvements to the Hypervisor implementation and error checking
> > - Connect some OpenTitan devices
> > - Changes to the sifive_u machine to support U-boot
> >
> > ----------------------------------------------------------------
>
> Hi; I'm afraid this fails "make check":
>
> MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-0} % 255 + 1))}
> QTEST_QEMU_BINARY=riscv32-softmmu/qemu-system-riscv32 QTEST_QEM
> U_IMG=qemu-img tests/qtest/qom-test -m=quick -k --tap < /dev/null |
> ./scripts/tap-driver.pl --test-name="qom-test"
> PASS 1 qom-test /riscv32/qom/opentitan
> PASS 2 qom-test /riscv32/qom/spike
> PASS 3 qom-test /riscv32/qom/virt
> PASS 4 qom-test /riscv32/qom/none
> qemu-system-riscv32:
> /home/petmay01/linaro/qemu-for-merges/hw/core/qdev.c:438:
> qdev_assert_realized_properly: Assertion `dev->parent_bus ||
> !dc->bus_type' failed.
> Broken pipe
> /home/petmay01/linaro/qemu-for-merges/tests/qtest/libqtest.c:175:
> kill_qemu() detected QEMU death from signal 6 (Aborted) (core dumped)
>
> This is a recently introduced check that all devices created
> get realized; probably somebody's added a new device in this
> pullreq but forgot a realize call.
Argh! The final rebase introduced this. Sorry, I'll send a v2.
Alistair
>
> thanks
> -- PMM
