The following changes since commit eefe34ea4b82c2b47abe28af4cc7247d51553626:
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20200617a'
into staging (2020-06-18 15:30:13 +0100)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200618-1
for you to fetch changes up to fad6a8463510ff5e0fb31bb451a6c3218a45d179:
hw/riscv: sifive_u: Add a dummy DDR memory controller device (2020-06-18
23:09:16 -0700)
----------------------------------------------------------------
This is a range of patches for RISC-V.
Some key points are:
- Generalise the CPU init functions
- Support the SiFive revB machine
- Improvements to the Hypervisor implementation and error checking
- Connect some OpenTitan devices
- Changes to the sifive_u machine to support U-boot
----------------------------------------------------------------
Alistair Francis (11):
sifive_e: Support the revB machine
target/riscv: Set access as data_load when validating stage-2 PTEs
target/riscv: Report errors validating 2nd-stage PTEs
target/riscv: Move the hfence instructions to the rvh decode
target/riscv: Implement checks for hfence
riscv/opentitan: Fix the ROM size
hw/char: Initial commit of Ibex UART
hw/intc: Initial commit of lowRISC Ibex PLIC
riscv/opentitan: Connect the PLIC device
riscv/opentitan: Connect the UART device
target/riscv: Use a smaller guess size for no-MMU PMP
Bin Meng (20):
riscv: Generalize CPU init routine for the base CPU
riscv: Generalize CPU init routine for the gcsu CPU
riscv: Generalize CPU init routine for the imacu CPU
riscv: Keep the CPU init routine names consistent
hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc*
functions
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc*
functions
hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
hw/riscv: sifive_u: Generate device tree node for OTP
hw/riscv: sifive_gpio: Clean up the codes
hw/riscv: sifive_gpio: Add a new 'ngpio' property
hw/riscv: sifive_u: Hook a GPIO controller
hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
hw/riscv: sifive_u: Add reset functionality
hw/riscv: sifive_u: Rename serial property get/set functions to a generic
name
hw/riscv: sifive_u: Add a new property msel for MSEL pin state
target/riscv: Rename IBEX CPU init routine
hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
hw/riscv: sifive_u: Support different boot source per MSEL pin state
hw/riscv: sifive_u: Sort the SoC memmap table entries
hw/riscv: sifive_u: Add a dummy DDR memory controller device
Ian Jiang (1):
riscv: Add helper to make NaN-boxing for FP register
include/hw/char/ibex_uart.h | 110 ++++++
include/hw/intc/ibex_plic.h | 63 ++++
include/hw/riscv/opentitan.h | 16 +
include/hw/riscv/sifive_e.h | 1 +
include/hw/riscv/sifive_gpio.h | 8 +-
include/hw/riscv/sifive_u.h | 27 ++
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 8 +-
hw/char/ibex_uart.c | 492 +++++++++++++++++++++++++
hw/intc/ibex_plic.c | 261 +++++++++++++
hw/riscv/opentitan.c | 71 +++-
hw/riscv/sifive_e.c | 60 ++-
hw/riscv/sifive_gpio.c | 45 ++-
hw/riscv/sifive_u.c | 157 ++++++--
target/riscv/cpu.c | 69 ++--
target/riscv/cpu_helper.c | 9 +-
target/riscv/insn_trans/trans_privileged.inc.c | 38 --
target/riscv/insn_trans/trans_rvf.inc.c | 17 +-
target/riscv/insn_trans/trans_rvh.inc.c | 37 ++
target/riscv/op_helper.c | 13 +
target/riscv/pmp.c | 14 +-
target/riscv/translate.c | 1 +
MAINTAINERS | 4 +
hw/char/Makefile.objs | 1 +
hw/intc/Makefile.objs | 1 +
hw/riscv/Kconfig | 4 +
26 files changed, 1350 insertions(+), 182 deletions(-)
create mode 100644 include/hw/char/ibex_uart.h
create mode 100644 include/hw/intc/ibex_plic.h
create mode 100644 hw/char/ibex_uart.c
create mode 100644 hw/intc/ibex_plic.c
create mode 100644 target/riscv/insn_trans/trans_rvh.inc.c
