On Wed, 3 Jun 2020 at 02:13, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> v2: Split out allocation_tag_mem. Handle atomicity of stores.
> v3: Add X[t] input to these insns; require pre-cleaned addresses.
> v5: Fix !32-byte aligned operation of st2g.
> v6: Fix op2 extract, stg pre/post-index, stores vs sp, commentary;
> use pre-computed ata.
> v7: Fix STZG iteration (stephen long)
> ---
> +static void disas_ldst_tag(DisasContext *s, uint32_t insn)
> +{
> + addr = read_cpu_reg_sp(s, rn, true);
> + if (index >= 0) {
> + /* pre-index or signed offset */
> + tcg_gen_addi_i64(addr, addr, offset);
> + }
> +
> + if (is_load) {
> + tcg_rt = cpu_reg(s, rt);
> + if (s->ata) {
> + gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt);
> + } else {
> + clean_addr = clean_data_tbi(s, addr);
> + gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8);
> + gen_address_with_allocation_tag0(tcg_rt, addr);
> + }
The pseudocode for LDG has an
address = Align(address, TAG_GRANULE);
in it. I don't see where in this code is the equivalent; have I missed it?
thanks
-- PMM
