On Mon, Jun 15, 2020 at 5:51 PM Bin Meng <bmeng...@gmail.com> wrote: > > From: Bin Meng <bin.m...@windriver.com> > > Per the SiFive manual, all E/U series CPU cores' reset vector is > at 0x1004. Update our codes to match the hardware. > > Signed-off-by: Bin Meng <bin.m...@windriver.com>
This commit breaks my Oreboot test. Oreboot starts in flash and we run the command with the `sifive_u,start-in-flash=true` machine. I have removed this and the later patches from the RISC-V branch. I want to send a PR today. After that I'll look into this. Alistair > > --- > > Changes in v2: > - rebase on https://github.com/alistair23/qemu riscv-to-apply.next branch > - rename SiFive E/U CPU init routine names > > hw/riscv/sifive_e.c | 10 ++++++---- > hw/riscv/sifive_u.c | 6 +++--- > target/riscv/cpu.c | 16 ++++++++-------- > 3 files changed, 17 insertions(+), 15 deletions(-) > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index d9a5c7b..d1d3bf1 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -98,14 +98,16 @@ static void sifive_e_machine_init(MachineState *machine) > memmap[SIFIVE_E_DTIM].base, main_mem); > > /* Mask ROM reset vector */ > - uint32_t reset_vec[2]; > + uint32_t reset_vec[4]; > > if (s->revb) { > - reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */ > + reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */ > } else { > - reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */ > + reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */ > } > - reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */ > + reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */ > + > + reset_vec[0] = reset_vec[3] = 0; > > /* copy in the reset vector in little_endian byte order */ > for (i = 0; i < sizeof(reset_vec) >> 2; i++) { > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index aaa5adb..0a86ffc 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -433,18 +433,18 @@ static void sifive_u_machine_init(MachineState *machine) > > /* reset vector */ > uint32_t reset_vec[8] = { > + 0x00000000, > 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ > - 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ > + 0x01c28593, /* addi a1, t0, %pcrel_lo(1b) */ > 0xf1402573, /* csrr a0, mhartid */ > #if defined(TARGET_RISCV32) > 0x0182a283, /* lw t0, 24(t0) */ > #elif defined(TARGET_RISCV64) > - 0x0182b283, /* ld t0, 24(t0) */ > + 0x0182e283, /* lwu t0, 24(t0) */ > #endif > 0x00028067, /* jr t0 */ > 0x00000000, > start_addr, /* start: .dword */ > - 0x00000000, > /* dtb: */ > }; > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 5f03458..391a0b9 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -134,20 +134,20 @@ static void riscv_base_cpu_init(Object *obj) > set_resetvec(env, DEFAULT_RSTVEC); > } > > -static void rvxx_gcsu_priv1_10_0_cpu_init(Object *obj) > +static void rvxx_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > - set_resetvec(env, DEFAULT_RSTVEC); > + set_resetvec(env, 0x1004); > } > > -static void rvxx_imacu_nommu_cpu_init(Object *obj) > +static void rvxx_sifive_e_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > - set_resetvec(env, DEFAULT_RSTVEC); > + set_resetvec(env, 0x1004); > qdev_prop_set_bit(DEVICE(obj), "mmu", false); > } > > @@ -578,13 +578,13 @@ static const TypeInfo riscv_cpu_type_infos[] = { > #if defined(TARGET_RISCV32) > DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), > - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_imacu_nommu_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), > - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, > rvxx_gcsu_priv1_10_0_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init), > #elif defined(TARGET_RISCV64) > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init), > - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_imacu_nommu_cpu_init), > - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, > rvxx_gcsu_priv1_10_0_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init), > #endif > }; > > -- > 2.7.4 > >
