Hello, On 6/12/20 12:30 AM, Havard Skinnemoen wrote: > This patch series models enough of the Nuvoton NPCM730 and NPCM750 SoCs to > boot > an OpenBMC image built for quanta-gsj. This includes device models for: > > - Global Configuration Registers > - Clock Control > - Timers > - Fuses > - Memory Controller > - Flash Controller
Do you have a git tree for this patchset ? > These modules, along with the existing Cortex A9 CPU cores and built-in > peripherals, are integrated into a NPCM730 or NPCM750 SoC, which in turn form > the foundation for the quanta-gsj and npcm750-evb machines, respectively. The > two SoCs are very similar; the only difference is that NPCM730 is missing some > peripherals that NPCM750 has, and which are not considered essential for > datacenter use (e.g. graphics controllers). For more information, see > > https://www.nuvoton.com/products/cloud-computing/ibmc/ > > Both quanta-gsj and npcm750-evb correspond to real boards supported by > OpenBMC. > While this initial series uses a stripped-down kernel for testing, future > series will be tested using OpenBMC images built from public sources. I'm > currently putting the finishing touches on flash controller support, which is > necessary to boot a full OpenBMC image, and will be enabled by the next > series. ok. It would be nice to be able to download the images from some site like we do for Aspeed. > The patches in this series were developed by Google and reviewed by Nuvoton. > We > will be maintaining the machine and peripheral support together. > > The data sheet for these SoCs is not generally available. Please let me know > if > more comments are needed to understand the device behavior. > > Changes since v1 (requested by reviewers): > > - Clarify the source of CLK reset values. > - Made smpboot a constant byte array, eliinated byte swapping. I have revived a PPC64 host. We might want to add the swapping back. > - NPCM7xxState now stores an array of ARMCPUs, not pointers to ARMCPUs. > - Clarify why EL3 is disabled. > - Introduce NPCM7XX_NUM_IRQ constant. > - Set the number of CPUs according to SoC variant, and disallow command line > overrides (i.e. you can no longer override the number of CPUs with the > -smp > parameter). This is trying to follow the spirit of > https://patchwork.kernel.org/patch/11595407/. > - Switch register operations to DEVICE_LITTLE_ENDIAN throughout. yes. We should do the same for Aspeed. > - Machine documentation added (new patch). Thanks, C. > Changes since v1 to support flash booting: > > - GCR reset value changes to get past memory initialization when booting > from flash (patches 2 and 5): > - INTCR2 now indicates that the DDR controller is initialized. > - INTCR3 is initialized according to DDR memory size. A realize() > method was implemented to achieve this. > - Refactor the machine initialization a bit to make it easier to drop in > machine-specific flash initialization (patch 6). > - Extend the series with additional patches to enable booting from flash: > - Boot ROM (through the -bios option). > - OTP (fuse) controller. > - Memory Controller stub (just enough to skip memory training). > - Flash controller. > - Board-specific flash initialization. > > Thanks for reviewing, > > Havard > > Havard Skinnemoen (12): > npcm7xx: Add config symbol > hw/misc: Add NPCM7xx System Global Control Registers device model > hw/misc: Add NPCM7xx Clock Controller device model > hw/timer: Add NPCM7xx Timer device model > hw/arm: Add NPCM730 and NPCM750 SoC models > hw/arm: Add two NPCM7xx-based machines > hw/arm: Load -bios image as a boot ROM for npcm7xx > hw/nvram: NPCM7xx OTP device model > hw/mem: Stubbed out NPCM7xx Memory Controller model > hw/ssi: NPCM7xx Flash Interface Unit device model > hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj > docs/system: Add Nuvoton machine documentation > > MAINTAINERS | 18 ++ > default-configs/arm-softmmu.mak | 1 + > docs/system/arm/nuvoton.rst | 89 ++++++ > docs/system/target-arm.rst | 1 + > hw/arm/Kconfig | 9 + > hw/arm/Makefile.objs | 1 + > hw/arm/npcm7xx.c | 449 ++++++++++++++++++++++++++++ > hw/arm/npcm7xx_boards.c | 168 +++++++++++ > hw/mem/Makefile.objs | 1 + > hw/mem/npcm7xx_mc.c | 83 ++++++ > hw/misc/Makefile.objs | 2 + > hw/misc/npcm7xx_clk.c | 216 ++++++++++++++ > hw/misc/npcm7xx_gcr.c | 211 +++++++++++++ > hw/misc/trace-events | 8 + > hw/nvram/Makefile.objs | 1 + > hw/nvram/npcm7xx_otp.c | 391 ++++++++++++++++++++++++ > hw/ssi/Makefile.objs | 1 + > hw/ssi/npcm7xx_fiu.c | 497 +++++++++++++++++++++++++++++++ > hw/ssi/trace-events | 9 + > hw/timer/Makefile.objs | 1 + > hw/timer/npcm7xx_timer.c | 437 +++++++++++++++++++++++++++ > hw/timer/trace-events | 5 + > include/hw/arm/npcm7xx.h | 106 +++++++ > include/hw/mem/npcm7xx_mc.h | 35 +++ > include/hw/misc/npcm7xx_clk.h | 65 ++++ > include/hw/misc/npcm7xx_gcr.h | 76 +++++ > include/hw/nvram/npcm7xx_otp.h | 93 ++++++ > include/hw/ssi/npcm7xx_fiu.h | 99 ++++++ > include/hw/timer/npcm7xx_timer.h | 95 ++++++ > 29 files changed, 3168 insertions(+) > create mode 100644 docs/system/arm/nuvoton.rst > create mode 100644 hw/arm/npcm7xx.c > create mode 100644 hw/arm/npcm7xx_boards.c > create mode 100644 hw/mem/npcm7xx_mc.c > create mode 100644 hw/misc/npcm7xx_clk.c > create mode 100644 hw/misc/npcm7xx_gcr.c > create mode 100644 hw/nvram/npcm7xx_otp.c > create mode 100644 hw/ssi/npcm7xx_fiu.c > create mode 100644 hw/timer/npcm7xx_timer.c > create mode 100644 include/hw/arm/npcm7xx.h > create mode 100644 include/hw/mem/npcm7xx_mc.h > create mode 100644 include/hw/misc/npcm7xx_clk.h > create mode 100644 include/hw/misc/npcm7xx_gcr.h > create mode 100644 include/hw/nvram/npcm7xx_otp.h > create mode 100644 include/hw/ssi/npcm7xx_fiu.h > create mode 100644 include/hw/timer/npcm7xx_timer.h >
