The Receive FIFO Read Enable command is used to request access to the
receive FIFO. When the command is finished, the controller will issue a
TCD interrupt and the number of available bytes will be available in tthe
RBCL register. Given that the visible receive FIFO window is used to
store characters as they come in, the only action that needs to be taken
is to raise the TCD interrupt (if this interrupt is enabled).
Signed-off-by: Jasper Lowell <jasper.low...@bt.com>
---
hw/char/escc2.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/char/escc2.c b/hw/char/escc2.c
index 5afb8aa6d9..8198b7fec3 100644
--- a/hw/char/escc2.c
+++ b/hw/char/escc2.c
@@ -762,6 +762,10 @@ static void escc2_channel_command(ESCC2ChannelState
*channel)
tmp &= ~(REGISTER_STAR_RFNE);
REGISTER_WRITE(channel, REGISTER_STAR, tmp);
}
+
+ if (command & REGISTER_CMDR_RFRD) {
+ escc2_channel_irq_event(channel, REGISTER_ISR0, REGISTER_ISR0_TCD);
+ }
}
static void escc2_mem_write(void *opaque, hwaddr addr, uint64_t value,
--
2.26.2
