On Mon, Jun 8, 2020 at 7:26 AM Bin Meng <bmeng...@gmail.com> wrote:
>
> From: Bin Meng <bin.m...@windriver.com>
>
> Move the flash and DRAM to the end of the SoC memmap table.
>
> Signed-off-by: Bin Meng <bin.m...@windriver.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index f64aa52..c94ff6f 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -80,10 +80,10 @@ static const struct MemmapEntry {
> [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
> [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
> [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
> - [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
> - [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
> [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
> + [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
> + [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> };
>
> #define OTP_SERIAL 1
> --
> 2.7.4
>
>
