чет, 11. јун 2020. у 11:50 Alex Bennée <alex.ben...@linaro.org> је написао/ла: > > > Aleksandar Markovic <aleksandar.qemu.de...@gmail.com> writes: > > > From: Huacai Chen <zltjiang...@gmail.com> > > > > Add more CP0 register for save/restore, including: EBase, XContext, > > PageGrain, PWBase, PWSize, PWField, PWCtl, Config*, KScratch1~KScratch6. > > > > Signed-off-by: Huacai Chen <che...@lemote.com> > > Co-developed-by: Jiaxun Yang <jiaxun.y...@flygoat.com> > > Reviewed-by: Aleksandar Markovic <aleksandar.qemu.de...@gmail.com> > > Signed-off-by: Aleksandar Markovic <aleksandar.qemu.de...@gmail.com> > > Message-Id: <1588501221-1205-6-git-send-email-che...@lemote.com> > > It seems while our mips cross build has been broken this commit has > caused a build regression: >
I'll take a look, but would ask Huacai to do the same. Thanks, Aleksandar > make docker-test-build@debian-mips-cross J=30 > > Results in: > > /tmp/qemu-test/src/target/mips/kvm.c: In function > 'kvm_mips_put_cp0_registers': > /tmp/qemu-test/src/target/mips/kvm.c:412:49: error: 'CP0C6_BPPASS' > undeclared (first use in this function); did you mean 'CP0C3_LPA'? > #define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ > ^~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro > 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:412:49: note: each undeclared > identifier is reported only once for each function it appears in > #define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ > ^~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro > 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:413:52: error: 'CP0C6_KPOS' undeclared > (first use in this function); did you mean 'CP0C3_IPLV'? > (0x3fU << CP0C6_KPOS) | \ > ^~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro > 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:414:49: error: 'CP0C6_KE' undeclared > (first use in this function); did you mean 'CP0C4_AE'? > (1U << CP0C6_KE) | \ > ^~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro > 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > > > > --- > > target/mips/kvm.c | 212 > > ++++++++++++++++++++++++++++++++++++++++++++++++++ > > target/mips/machine.c | 6 +- > > 2 files changed, 216 insertions(+), 2 deletions(-) > > > > diff --git a/target/mips/kvm.c b/target/mips/kvm.c > > index de3e26e..96cfa10 100644 > > --- a/target/mips/kvm.c > > +++ b/target/mips/kvm.c > > @@ -245,10 +245,16 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, > > int level) > > (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) > > > > #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) > > +#define KVM_REG_MIPS_CP0_RANDOM MIPS_CP0_32(1, 0) > > #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) > > #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) > > #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) > > +#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) > > +#define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5) > > +#define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6) > > +#define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7) > > #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) > > +#define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6) > > #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) > > #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) > > #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) > > @@ -258,13 +264,22 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, > > int level) > > #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) > > #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) > > #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) > > +#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) > > #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) > > #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) > > #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) > > #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) > > #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) > > #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) > > +#define KVM_REG_MIPS_CP0_CONFIG6 MIPS_CP0_32(16, 6) > > +#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) > > #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) > > +#define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2) > > +#define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3) > > +#define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4) > > +#define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5) > > +#define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6) > > +#define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7) > > > > static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, > > int32_t *addr) > > @@ -394,6 +409,29 @@ static inline int kvm_mips_get_one_ureg64(CPUState > > *cs, uint64_t reg_id, > > (1U << CP0C5_UFE) | \ > > (1U << CP0C5_FRE) | \ > > (1U << CP0C5_UFR)) > > +#define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ > > + (0x3fU << CP0C6_KPOS) | \ > > + (1U << CP0C6_KE) | \ > > + (1U << CP0C6_VTLBONLY) | \ > > + (1U << CP0C6_LASX) | \ > > + (1U << CP0C6_SSEN) | \ > > + (1U << CP0C6_DISDRTIME) | \ > > + (1U << CP0C6_PIXNUEN) | \ > > + (1U << CP0C6_SCRAND) | \ > > + (1U << CP0C6_LLEXCEN) | \ > > + (1U << CP0C6_DISVC) | \ > > + (1U << CP0C6_VCLRU) | \ > > + (1U << CP0C6_DCLRU) | \ > > + (1U << CP0C6_PIXUEN) | \ > > + (1U << CP0C6_DISBLKLYEN) | \ > > + (1U << CP0C6_UMEMUALEN) | \ > > + (1U << CP0C6_SFBEN) | \ > > + (1U << CP0C6_FLTINT) | \ > > + (1U << CP0C6_VLTINT) | \ > > + (1U << CP0C6_DISBTB) | \ > > + (3U << CP0C6_STPREFCTL) | \ > > + (1U << CP0C6_INSTPREF) | \ > > + (1U << CP0C6_DATAPREF)) > > It seems a lot of the defines here aren't in this commit. Was one missed? > > -- > Alex Bennée
