Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/cpu.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 37b7cc2c9c..6395918524 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -39,6 +39,7 @@
#include "kvm_arm.h"
#include "disas/capstone.h"
#include "fpu/softfloat.h"
+#include "qemu/guest-random.h"
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -191,6 +192,22 @@ static void arm_cpu_reset(DeviceState *dev)
/* Enable all PAC keys. */
env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
SCTLR_EnDA | SCTLR_EnDB);
+ /* Enable MTE */
+ if (cpu_isar_feature(aa64_mte, cpu)) {
+ /* Enable tag access, but leave TCF0 as No Effect (0). */
+ env->cp15.sctlr_el[1] |= SCTLR_ATA0;
+ /*
+ * Exclude all tags, so that tag 0 is always used.
+ * This corresponds to Linux current->thread.gcr_incl = 0.
+ */
+ env->cp15.gcr_el1 = 0xffff;
+ /* If RGSR == 0, NextRandomTagBit will always produce 0. */
+ do {
+ qemu_guest_getrandom_nofail(&env->cp15.rgsr_el1,
+ sizeof(env->cp15.rgsr_el1));
+ env->cp15.rgsr_el1 &= 0xffff0fu;
+ } while (env->cp15.rgsr_el1 == 0);
+ }
/* and to the FP/Neon instructions */
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
/* and to the SVE instructions */
--
2.25.1
