On Fri, May 8, 2020 at 3:21 AM Alistair Francis
<alistair.fran...@wdc.com> wrote:
>
> The ISA specific Spike machines have been deprecated in QEMU since 4.1,
> let's finally remove them.
>
> Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
> Reviewed-by: Philippe Mathieu-Daudé <phi...@redhat.com>
> ---
> hw/riscv/spike.c | 217 ---------------------------------------
> include/hw/riscv/spike.h | 6 +-
> 2 files changed, 2 insertions(+), 221 deletions(-)
>
[snip]
> diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
> index dc770421bc..b98cfea0e4 100644
> --- a/include/hw/riscv/spike.h
> +++ b/include/hw/riscv/spike.h
> @@ -39,11 +39,9 @@ enum {
> };
>
> #if defined(TARGET_RISCV32)
> -#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
> -#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
> +#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_SIFIVE_U34
> #elif defined(TARGET_RISCV64)
> -#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
> -#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
> +#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_SIFIVE_U54
> #endif
On a second thought, I think we should not use the SIFIVE CPU type
here for Spike.
It should use the one that is used by 'virt', eg: TYPE_RISCV_CPU_BASE{32,64}
Regards,
Bin
