/*
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| Bits | Name | Description
|
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 32 | FE | Floating-point exception summary. Every floating-point
instruction, except mtfsfi and mtfsf, implicitly sets FX |
| | | if that instruction causes any of the floating-point
exception bits in the FPSCR to change from 0 to 1. mcrfs, |
| | | mtfsfi, mtfsf, mtfsb0, and mtfsb1 can alter FPSCR[FX]
explicitly. |
| | | Note: (Programming) FPSCR[FX] is defined not to be
altered implicitly by mtfsfi and mtfsf because |
| | | permitting these instructions to alter FPSCR[FX]
implicitly could cause a paradox. An example is an |
| | | mtfsfi or mtfsf that supplies 0 for FPSCR[FX] and 1 for
FPSCR[OX] and executes when FPSCR[OX] = 0. |
| | | See also the programming notes with the definition of
these two instructions. |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 33 | FEX | Floating-point enabled exception summary. FEX is the OR
of all the floating-point exception bits masked by |
| | | their respective enable bits. mcrfs, mtfsfi, mtfsf,
mtfsb0, and mtfsb1 cannot alter FPSCR[FEX] explicitly. |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 34 | VX | Floating-point invalid operation exception summary. VX
is the OR of all the invalid operation exception bits. |
| | | mcrfs, mtfsfi, mtfsf, mtfsb0, and mtfsb1 cannot alter
FPSCR[VX] explicitly. |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 35 | OX | Floating-point overflow exception. See Section
5.6.1.7.3, “Overflow Exception.” |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 36 | UX | Floating-point underflow exception. See Section
5.6.1.7.4, “Underflow Exception.” |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 37 | ZX | Floating-Point zero divide exception. See Section
5.6.1.7.2, “Zero Divide Exception.” |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 38 | XX | Floating-point inexact exception. See Section 5.6.1.7.5,
“Inexact Exception.” |
| | | FPSCR[XX] is a sticky version of FPSCR[FI] (see below).
Thus the following rules completely describe how |
| | | FPSCR[XX] is set by a given instruction:
|
| | | • If the instruction affects FPSCR[FI], the new
FPSCR[XX] value is obtained by ORing the old value of |
| | | FPSCR[XX] with the new value of FPSCR[FI].
|
| | | • If the instruction does not affect FPSCR[FI], the
value of FPSCR[XX] is unchanged |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 39 | VXSNAN | Floating-point invalid operation exception (SNAN). See
Section 5.6.1.7.1, “Invalid Operation Exception.” |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 40 | VXISI | floating-point invalid operation exception (∞ − ∞). See
Section 5.6.1.7.1, “Invalid Operation Exception.”. |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 41 | VXIDI | Floating-point invalid operation exception ( ∞ ÷ ∞).See
Section 5.6.1.7.1, “Invalid Operation Exception.”. |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 42 | VXZDZ | Floating-point invalid operation exception (0 ÷ 0) See
Section 5.6.1.7.1, “Invalid Operation Exception.”. |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 43 | VXIMZ | Floating-point invalid operation exception (∞ ×0). See
Section 5.6.1.7.1, “Invalid Operation Exception.”. |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 44 | VXVC | Floating-point invalid operation exception (invalid
compare). See Section 5.6.1.7.1, “Invalid Operation Exception.”. |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 45 | FR | Floating-point fraction rounded. The last arithmetic or
rounding and conversion instruction incremented the |
| | | fraction during rounding. See Section 4.4.3.6,
“Rounding.” This bit is not sticky. |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 46 | FI | Floating-point fraction inexact. The last arithmetic or
rounding and conversion instruction either produced an |
| | | inexact result during rounding or caused a disabled
overflow exception. See Section 4.4.3.6, “Rounding.” FI is |
| | | not sticky. See the definition of FPSCR[XX], above,
regarding the relationship between FI and XX. |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 47-51 | FPRF | Floating-point result flags. Arithmetic, rounding, and
convert from integer instructions set FPRF based on the |
| | | result placed into the target register and on the
target precision, except that if any portion of the result is |
| | | undefined, the value placed into FPRF is undefined.
Floating-point compare instructions set FPRF based on |
| | | the relative values of the operands compared. For
convert to integer instructions, the value placed into FPRF |
| | | is undefined. See Table 4-9.
|
| | | Note: (Programming) A single-precision operation that
produces a denormalized result sets FPRF to indicate |
| | | a denormalized number. When possible, single-precision
denormalized numbers are represented in |
| | | normalized double format in the target register.
|
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 47 | C | Floating-point result class descriptor. Arithmetic,
rounding, and conversion instructions may set this bit with |
| | | the FPCC bits, to indicate the class of the result as
shown in Figure 4-9. |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 48-51 | FPCC | Floating-point condition code. Floating-point Compare
instructions set one of the FPCC bits and clear the |
| | | other three FPCC bits. Arithmetic, rounding, and
conversion instructions may set the FPCC bits with the C bit |
| | | to indicate the class of the result. In this case, the
three high-order FPCC bits retain their relational |
| | | significance indicating that the value is less than,
greater than, or equal to zero. |
| | | 48 Floating-point less than or negative (FL or <)
|
| | | 49 Floating-point greater than or positive (FG or >)
|
| | | 50 Floating-point equal or zero (FE or =)
|
| | | 51 Floating-point unordered or NaN (FU or ?)
|
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 52 | — | Reserved, should be cleared.
|
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 53 | VXSOFT | Floating-point invalid operation exception (software
request). Can be altered only by mcrfs, mtfsfi, mtfsf, |
| | | mtfsb0, or mtfsb1
|
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 54 | VXSQRT | Floating-point invalid operation exception (invalid
square root). |
| | | Note that VXSQRT is defined even for implementations
that do not support either of the two optional |
| | | instructions that set it, fsqrt[.] and frsqrte[.].
Defining it for all implementations gives software a standard |
| | | interface for handling square root exceptions. If an
implementation does not support fsqrt[.] or frsqrte[.], |
| | | software can simulate the instruction and set VXSQRT to
reflect the exception. |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 55 | VXCVI | Floating-point invalid operation exception (invalid
integer convert) |
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 56 | VE | Floating-point invalid operation exception enable
|
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 57 | OE | Floating-point overflow exception enable
|
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 58 | UE | Floating-point underflow exception enable
|
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 59 | ZE | Floating-point zero divide exception enable
|
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 60 | XE | Floating-point inexact exception enable
|
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 61 | NI | Floating-point non-IEEE mode. If NI = 1, the remaining
FPSCR bits may have meanings other than those given |
| | | in this document and results of floating-point
operations need not conform to IEEE 754. If the |
| | | IEEE-754-conforming result of a floating-point
operation would be a denormalized number, the result of that |
| | | operation is 0 (with the same sign as the denormalized
number) if FPSCR[NI] = 1 and other requirements |
| | | specified in the user’s manual for the implementation
are met. The other effects of setting NI may differ among |
| | | implementations.
|
| | | Setting NI is intended to permit results to be
approximate and to cause performance to be more predictable |
| | | and less data-dependent than when NI = 0. For example,
in non-IEEE mode, an implementation returns 0 |
| | | instead of a denormalized number and may return a large
number instead of an infinity. In non-IEEE mode an |
| | | implementation should provide a means for ensuring that
all results are produced without software assistance |
| | | (that is, without causing an enabled exception type
program interrupt or a floating-point unimplemented |
| | | instruction exception type program interrupt and
without invoking an emulation assist). The means may be |
| | | controlled by one or more other FPSCR bits (recall that
the other FPSCR bits have implementation-dependent |
| | | meanings if NI = 1).
|
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
| 62-63 | RN | Floating-point rounding control (RN).
|
| | | 00 Round to nearest
|
| | | 01 Round toward zero
|
| | | 10 Round toward +infinity
|
| | | 11 Round toward –infinity
|
+-------+--------+----------------------------------------------------------------------------------------------------------------------+
*/
static int ieee_ex_to_ppc(int fexcp)
{
int ret = 0;
/* Question? TODO: How to handling Invalid Operation Exception. */
if (fexcp & float_flag_invalid) {
ret |= VX;
}
if (fexcp & float_flag_overflow) {
ret |= FP_OX;
}
if (fexcp & float_flag_underflow) {
ret |= FP_UX;
}
if (fexcp & float_flag_divbyzero) {
ret |= FP_ZX;
}
if (fexcp & float_flag_inexact) {
ret |= FP_XX;
ret |= FP_FI;
}
return ret;
}
void helper_update_fpscr(CPUPPCState *env, int op, uintptr_t retaddr)
{
int tmp = get_float_exception_flags(&env->fp_status);
if (tmp) {
tmp = ieee_ex_to_ppc(tmp);
set_float_exception_flags(0, &env->fp_status);
if (tmp) {
env->fpscr |= tmp;
if (fp_exceptions_enabled(env) && (env->fpscr & FP_FEX)) {
if (env->fpscr & FP_VE) {
raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_FP | op, retaddr);
}
}
}
}
}
I found the fpscr are really complicated, especially abount Invalid
Operation Exception.
And fp_status can not represent all the Invalid Operation Exception flags.
What I need to do to represent all the Invalid Operation Exception
--
此致
礼
罗勇刚
Yours
sincerely,
Yonggang Luo
