Ping for code review, since 5.0 is nearly out the door... thanks -- PMM
On Mon, 30 Mar 2020 at 22:04, Peter Maydell <peter.mayd...@linaro.org> wrote: > > This is obviously not 5.0 material, but I figured it would be better > to push it out for review now rather than hang on to it and forget... > > TTS2UXN is an ARMv8.2 extension which changes the 'XN' field in stage > 2 translation table descriptors from just bit [54] to bits [54:53], > allowing stage 2 to control execution permissions separately for EL0 > and EL1. > > For QEMU this had the potential to be awkward, because it means that > the stage 2 translation now depends on whether it's being used > for an EL0 or an EL1 stage 1 access (the address doesn't change > but the access permissions do). Fortunately, although we allocated > a QEMU TLB/MMU index for Stage 2, we never actually look anything > up in the TLB. So patch 1 turns ARMMMUIdx_Stage2 into a 'NOTLB' > index (ie one without a QEMU TLB), thus avoiding the complication > of splitting it into separate Stage2-for-EL0 and Stage2-for-EL1 > indexes. Once we've done that the actual implementation is pretty > trivial -- we just need to plumb an extra 's1_is_el0' argument > into get_phys_addr_lpae(), and then use it to decide what to do. > > Peter Maydell (4): > target/arm: Don't use a TLB for ARMMMUIdx_Stage2 > target/arm: Use enum constant in get_phys_addr_lpae() call > target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae() > target/arm: Implement ARMv8.2-TTS2UXN > > target/arm/cpu-param.h | 2 +- > target/arm/cpu.h | 36 ++++++-- > target/arm/cpu.c | 1 + > target/arm/cpu64.c | 2 + > target/arm/helper.c | 183 ++++++++++++++++------------------------- > 5 files changed, 107 insertions(+), 117 deletions(-)
