Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
---
target/riscv/insn32.decode | 6 +-
.../riscv/insn_trans/trans_privileged.inc.c | 40 -------------
target/riscv/insn_trans/trans_rvh.inc.c | 57 +++++++++++++++++++
target/riscv/translate.c | 1 +
4 files changed, 62 insertions(+), 42 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvh.inc.c
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b883672e63..05266f5a36 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -77,8 +77,6 @@ uret 0000000 00010 00000 000 00000 1110011
sret 0001000 00010 00000 000 00000 1110011
mret 0011000 00010 00000 000 00000 1110011
wfi 0001000 00101 00000 000 00000 1110011
-hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
-hfence_bvma 0010001 ..... ..... 000 00000 1110011 @hfence_bvma
sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
@@ -207,3 +205,7 @@ fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
+
+# *** RV32H Base Instruction Set ***
+hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
+hfence_bvma 0010001 ..... ..... 000 00000 1110011 @hfence_bvma
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c
b/target/riscv/insn_trans/trans_privileged.inc.c
index 76c2fad71c..c187ead774 100644
--- a/target/riscv/insn_trans/trans_privileged.inc.c
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -103,43 +103,3 @@ static bool trans_sfence_vm(DisasContext *ctx,
arg_sfence_vm *a)
#endif
return false;
}
-
-static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
-{
-#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
- has_ext(ctx, RVH)) {
- /* Hpervisor extensions exist */
- /*
- * if (env->priv == PRV_M ||
- * (env->priv == PRV_S &&
- * !riscv_cpu_virt_enabled(env) &&
- * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
- */
- gen_helper_tlb_flush(cpu_env);
- return true;
- /* } */
- }
-#endif
- return false;
-}
-
-static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a)
-{
-#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
- has_ext(ctx, RVH)) {
- /* Hpervisor extensions exist */
- /*
- * if (env->priv == PRV_M ||
- * (env->priv == PRV_S &&
- * !riscv_cpu_virt_enabled(env) &&
- * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
- */
- gen_helper_tlb_flush(cpu_env);
- return true;
- /* } */
- }
-#endif
- return false;
-}
diff --git a/target/riscv/insn_trans/trans_rvh.inc.c
b/target/riscv/insn_trans/trans_rvh.inc.c
new file mode 100644
index 0000000000..2e91d6ae57
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvh.inc.c
@@ -0,0 +1,57 @@
+/*
+ * RISC-V translation routines for the RVXI Base Integer Instruction Set.
+ *
+ * Copyright (c) 2020 Western Digital
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+ if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
+ has_ext(ctx, RVH)) {
+ /* Hpervisor extensions exist */
+ /*
+ * if (env->priv == PRV_M ||
+ * (env->priv == PRV_S &&
+ * !riscv_cpu_virt_enabled(env) &&
+ * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
+ */
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+ /* } */
+ }
+#endif
+ return false;
+}
+
+static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+ if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
+ has_ext(ctx, RVH)) {
+ /* Hpervisor extensions exist */
+ /*
+ * if (env->priv == PRV_M ||
+ * (env->priv == PRV_S &&
+ * !riscv_cpu_virt_enabled(env) &&
+ * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
+ */
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+ /* } */
+ }
+#endif
+ return false;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 43bf7e39a6..ce71ca7a92 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -711,6 +711,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
#include "insn_trans/trans_rva.inc.c"
#include "insn_trans/trans_rvf.inc.c"
#include "insn_trans/trans_rvd.inc.c"
+#include "insn_trans/trans_rvh.inc.c"
#include "insn_trans/trans_privileged.inc.c"
/* Include the auto-generated decoder for 16 bit insn */
--
2.26.2
