On 23 June 2011 12:13, Jamie Iles <ja...@jamieiles.com> wrote: > + case ARM_CPUID_ARM1176: > + set_feature(env, ARM_FEATURE_V4T); > + set_feature(env, ARM_FEATURE_V5); > + set_feature(env, ARM_FEATURE_V6); > + set_feature(env, ARM_FEATURE_V6K); > + set_feature(env, ARM_FEATURE_AUXCR); > + memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t)); > + memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t)); > + env->cp15.c0_cachetype = 0x1dd20d2; > + env->cp15.c1_sys = 0x00050078; > + break;
Looking at the other cores we model it seems like it would be more consistent to model the 1176JZF-S, ie the variant with VFP; we generally seem to have just one variant of each core and it's the one with all the bells and whistles. Otherwise looks good (I haven't actually checked all the ID register values ;-)) -- PMM
