On Tue, Mar 17, 2020 at 8:51 AM LIU Zhiwei <zhiwei_...@c-sky.com> wrote: > > Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com> > Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/helper.h | 22 ++++++++++++ > target/riscv/insn32.decode | 7 ++++ > target/riscv/insn_trans/trans_rvv.inc.c | 9 +++++ > target/riscv/vector_helper.c | 45 +++++++++++++++++++++++++ > 4 files changed, 83 insertions(+) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 098288df76..1f0d3d60e3 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -643,3 +643,25 @@ DEF_HELPER_6(vnmsub_vx_b, void, ptr, ptr, tl, ptr, env, > i32) > DEF_HELPER_6(vnmsub_vx_h, void, ptr, ptr, tl, ptr, env, i32) > DEF_HELPER_6(vnmsub_vx_w, void, ptr, ptr, tl, ptr, env, i32) > DEF_HELPER_6(vnmsub_vx_d, void, ptr, ptr, tl, ptr, env, i32) > + > +DEF_HELPER_6(vwmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vwmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vwmaccu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vwmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vwmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vwmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vwmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vwmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vwmaccsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vwmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vwmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vwmaccu_vx_w, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vwmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vwmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vwmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vwmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vwmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vwmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vwmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vwmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32) > +DEF_HELPER_6(vwmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index b49b60aea1..9735ac3565 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -393,6 +393,13 @@ vmadd_vv 101001 . ..... ..... 010 ..... 1010111 > @r_vm > vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm > vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm > vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm > +vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm > +vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm > +vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm > +vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm > +vwmaccsu_vv 111110 . ..... ..... 010 ..... 1010111 @r_vm > +vwmaccsu_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm > +vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm > > vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm > vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > diff --git a/target/riscv/insn_trans/trans_rvv.inc.c > b/target/riscv/insn_trans/trans_rvv.inc.c > index 6d2ccbd615..269d04c7fb 100644 > --- a/target/riscv/insn_trans/trans_rvv.inc.c > +++ b/target/riscv/insn_trans/trans_rvv.inc.c > @@ -1490,3 +1490,12 @@ GEN_OPIVX_TRANS(vmacc_vx, opivx_check) > GEN_OPIVX_TRANS(vnmsac_vx, opivx_check) > GEN_OPIVX_TRANS(vmadd_vx, opivx_check) > GEN_OPIVX_TRANS(vnmsub_vx, opivx_check) > + > +/* Vector Widening Integer Multiply-Add Instructions */ > +GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check) > +GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check) > +GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check) > +GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx) > +GEN_OPIVX_WIDEN_TRANS(vwmacc_vx) > +GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx) > +GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx) > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index f65ed6abbc..5adce9e0a3 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -1954,3 +1954,48 @@ GEN_VEXT_VX(vnmsub_vx_b, 1, 1, clearb) > GEN_VEXT_VX(vnmsub_vx_h, 2, 2, clearh) > GEN_VEXT_VX(vnmsub_vx_w, 4, 4, clearl) > GEN_VEXT_VX(vnmsub_vx_d, 8, 8, clearq) > + > +/* Vector Widening Integer Multiply-Add Instructions */ > +RVVCALL(OPIVV3, vwmaccu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MACC) > +RVVCALL(OPIVV3, vwmaccu_vv_h, WOP_UUU_H, H4, H2, H2, DO_MACC) > +RVVCALL(OPIVV3, vwmaccu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MACC) > +RVVCALL(OPIVV3, vwmacc_vv_b, WOP_SSS_B, H2, H1, H1, DO_MACC) > +RVVCALL(OPIVV3, vwmacc_vv_h, WOP_SSS_H, H4, H2, H2, DO_MACC) > +RVVCALL(OPIVV3, vwmacc_vv_w, WOP_SSS_W, H8, H4, H4, DO_MACC) > +RVVCALL(OPIVV3, vwmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, DO_MACC) > +RVVCALL(OPIVV3, vwmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, DO_MACC) > +RVVCALL(OPIVV3, vwmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, DO_MACC) > +GEN_VEXT_VV(vwmaccu_vv_b, 1, 2, clearh) > +GEN_VEXT_VV(vwmaccu_vv_h, 2, 4, clearl) > +GEN_VEXT_VV(vwmaccu_vv_w, 4, 8, clearq) > +GEN_VEXT_VV(vwmacc_vv_b, 1, 2, clearh) > +GEN_VEXT_VV(vwmacc_vv_h, 2, 4, clearl) > +GEN_VEXT_VV(vwmacc_vv_w, 4, 8, clearq) > +GEN_VEXT_VV(vwmaccsu_vv_b, 1, 2, clearh) > +GEN_VEXT_VV(vwmaccsu_vv_h, 2, 4, clearl) > +GEN_VEXT_VV(vwmaccsu_vv_w, 4, 8, clearq) > + > +RVVCALL(OPIVX3, vwmaccu_vx_b, WOP_UUU_B, H2, H1, DO_MACC) > +RVVCALL(OPIVX3, vwmaccu_vx_h, WOP_UUU_H, H4, H2, DO_MACC) > +RVVCALL(OPIVX3, vwmaccu_vx_w, WOP_UUU_W, H8, H4, DO_MACC) > +RVVCALL(OPIVX3, vwmacc_vx_b, WOP_SSS_B, H2, H1, DO_MACC) > +RVVCALL(OPIVX3, vwmacc_vx_h, WOP_SSS_H, H4, H2, DO_MACC) > +RVVCALL(OPIVX3, vwmacc_vx_w, WOP_SSS_W, H8, H4, DO_MACC) > +RVVCALL(OPIVX3, vwmaccsu_vx_b, WOP_SSU_B, H2, H1, DO_MACC) > +RVVCALL(OPIVX3, vwmaccsu_vx_h, WOP_SSU_H, H4, H2, DO_MACC) > +RVVCALL(OPIVX3, vwmaccsu_vx_w, WOP_SSU_W, H8, H4, DO_MACC) > +RVVCALL(OPIVX3, vwmaccus_vx_b, WOP_SUS_B, H2, H1, DO_MACC) > +RVVCALL(OPIVX3, vwmaccus_vx_h, WOP_SUS_H, H4, H2, DO_MACC) > +RVVCALL(OPIVX3, vwmaccus_vx_w, WOP_SUS_W, H8, H4, DO_MACC) > +GEN_VEXT_VX(vwmaccu_vx_b, 1, 2, clearh) > +GEN_VEXT_VX(vwmaccu_vx_h, 2, 4, clearl) > +GEN_VEXT_VX(vwmaccu_vx_w, 4, 8, clearq) > +GEN_VEXT_VX(vwmacc_vx_b, 1, 2, clearh) > +GEN_VEXT_VX(vwmacc_vx_h, 2, 4, clearl) > +GEN_VEXT_VX(vwmacc_vx_w, 4, 8, clearq) > +GEN_VEXT_VX(vwmaccsu_vx_b, 1, 2, clearh) > +GEN_VEXT_VX(vwmaccsu_vx_h, 2, 4, clearl) > +GEN_VEXT_VX(vwmaccsu_vx_w, 4, 8, clearq) > +GEN_VEXT_VX(vwmaccus_vx_b, 1, 2, clearh) > +GEN_VEXT_VX(vwmaccus_vx_h, 2, 4, clearl) > +GEN_VEXT_VX(vwmaccus_vx_w, 4, 8, clearq) > -- > 2.23.0 >
